7D01: Difference between revisions

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title=Tektronix 7D01 |
title=Tektronix 7D01 |
summary=Logic Analyzer |
summary=Logic Analyzer |
image=Tek-7704a-7D01.jpg |  
image=Tek 7D01 Front 2.jpg |  
caption=7D01 in a [[7704A]] mainframe (catalog picture) |
caption=Tektronix 7D01 without display formatter |
introduced=1977 |
introduced=1976 |
discontinued=1985 |
discontinued=1985 |
series=[[7000-series scopes]]|
series=[[7000-series scopes]]|
Line 11: Line 11:
* [http://w140.com/tekscope_1976vol8no2_7d01.pdf 7D01 Article in 1976 Volume 8 Number 2 Tekscope (PDF)]
* [http://w140.com/tekscope_1976vol8no2_7d01.pdf 7D01 Article in 1976 Volume 8 Number 2 Tekscope (PDF)]
}}
}}
The '''Tektronix 7D01''' is a logic analyzer plug-in for the [[7000-series scopes]].
The '''Tektronix 7D01''' is a logic analyzer plug-in for the [[7000-series scopes]]. Compatible extension modules
include the [[DF1]] and [[DF2]] display formatters and the [[DL2]] latch (glitch detector). The 7D01 takes two [[P6451]] 8+1 channel probes.


==Specifications==
{{BeginSpecs}}
[[Category:Specifications needed]] ''please add''
{{Spec | Channels |
* 4 channels at 1016 bits/channel, maximum external clock period 10 ns (100 MHz)
* 8 channels at 508 bits/channel, maximum external clock period 20 ns (50 MHz)
* 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)
}}
{{Spec | Sampling Rate | 10 ns to 5 ms per sample (1—2—5) or external clock up to 50 MHz}}
{{Spec | Trigger Sources |
* external
* channel 0 data
* 16 channel word recognizer
* manual
}}
{{EndSpecs}}
 
==Notes==
'''Note about external clock rates''' (from Jim Mauck):  
 
''When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.''
 
==Links==
 
* [http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/logicanalyzer_7D01.htm  7D01 @ amplifier.cd]
* [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com]


==Pictures==
==Pictures==
[[Category:Image needed]] ''please add''


<gallery>
<gallery>
Image:Tek-7704a-7D01.jpg        | 7D01 in [[7704A]] mainframe
Tek-7704a-7D01.jpg        | 7D01 in [[7704A]] mainframe
[[File:Tek-7D01-front.jpg       | 7D01 front]]
Tek 7d01 and df1 in 7313.jpg|7D01 and [[DF1]] in [[7313]]
Tek df2 7d01 lit.jpg
Tek_7D01_Front.jpg        | 7D01+[[DF1]] Front
Tek_7D01_Left.jpg        | 7D01 Left
Tek_7D01_Right.jpg        | 7D01 Right
Tek_7D01_Bottom.jpg      | 7D01 Bottom
Tek_7D01_rear.jpg        | 7D01 Rear (back plate removed)
Tek_7D01_Cursor.jpg      | 7D01 Cursor Board
Tek_7D01_Memory.jpg      | 7D01 Memory Board
Tek_7D01_timing.jpg      | 7D01 Timing Diagram
Tek_7D01-DF01_timing.jpg  | 7D01 + [[DF1]] Timing Diagram
Tek_7D01-DF01_table.jpg   | 7D01 + [[DF1]] State Table
</gallery>
</gallery>


[[Category:7000 series special-function plugins]]
[[Category:7000 series special-function plugins]]
[[Category:Logic Analyzers]]
[[Category:Logic Analyzers]]

Revision as of 05:24, 7 February 2018

Template:Plugin Sidebar 2 The Tektronix 7D01 is a logic analyzer plug-in for the 7000-series scopes. Compatible extension modules include the DF1 and DF2 display formatters and the DL2 latch (glitch detector). The 7D01 takes two P6451 8+1 channel probes.

Key Specifications

Channels
  • 4 channels at 1016 bits/channel, maximum external clock period 10 ns (100 MHz)
  • 8 channels at 508 bits/channel, maximum external clock period 20 ns (50 MHz)
  • 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)
Sampling Rate 10 ns to 5 ms per sample (1—2—5) or external clock up to 50 MHz
Trigger Sources
  • external
  • channel 0 data
  • 16 channel word recognizer
  • manual

Notes

Note about external clock rates (from Jim Mauck):

When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.

Links

Pictures