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7D14: Difference between revisions
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A differential FET buffer + bipolar amplifier stage drives a counter gate that uses a 10 mA [[tunnel diode]] as the switching element. | A differential FET buffer + bipolar amplifier stage drives a counter gate that uses a 10 mA [[tunnel diode]] as the switching element. | ||
The first decade is implemented as a divide-by-2 ECL flip-flop ( | The first counter decade is implemented as a divide-by-2 ECL flip-flop (U329) followed by a five-stage ring counter made with discrete transistor pairs (note circular layout) and some logic to BCD-encode the count result. | ||
In early 7D14 units (board 388-1825-00), U329 was a Tek made IC, [[155-0046-00]], which was not used in other instruments. From SN B050000 on, a standard ECL part ([[156-0377-00]]) was used on a a redesigned high-frequency counter board (670-0993-01). | |||
The following seven counter stages are conventional TTL decade ripple counters (N8292A). | The following seven counter stages are conventional TTL decade ripple counters (N8292A). | ||
The counter outputs are multiplexed onto a common 4-bit bus using open-collector NAND gates under control of the mainframe's [[7000 series readout system|readout system]]. The multiplexed digit value feeds a D/A converter (Tek [[155-0038-01]]) that in turn drives the analog row and column returns to the readout system. A separate blanking logic eliminates leading zeroes and displays a ">" sign in the leftmost column if the counter overflows. | The counter outputs are multiplexed onto a common 4-bit bus using open-collector NAND gates under control of the mainframe's [[7000 series readout system|readout system]]. The multiplexed digit value feeds a D/A converter (Tek [[155-0038-01]]) that in turn drives the analog row and column returns to the readout system. A separate blanking logic eliminates leading zeroes and displays a ">" sign in the leftmost column if the counter overflows. | ||
==Links== | ==Links== | ||