067-0587-02: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
mNo edit summary |
||
| Line 33: | Line 33: | ||
The clock is delayed, amplified and limited, then fed to a Schottky-diode based pulse shaper with L-C compensating networks. The output pulse has a rise time of max. 150 picoseconds with less than 2% aberrations. | The clock is delayed, amplified and limited, then fed to a Schottky-diode based pulse shaper with L-C compensating networks. The output pulse has a rise time of max. 150 picoseconds with less than 2% aberrations. | ||
The staircase generator for Gain mode is implemented using a 4 bit count and multiplexer. The 0-volt step (No. 6) is held for five counts, producing a brighter trace to allow easy alignment | The staircase generator for Gain mode is implemented using a 4 bit count and multiplexer. The 0-volt step (No. 6) is held for five counts, producing a brighter trace to allow easy alignment with the center of the screen. | ||
For bandwidth measurements, there is a leveler circuit with a differential diode detector controlling an amplifier's gain in an AGC loop. | For bandwidth measurements, there is a leveler circuit with a differential diode detector controlling an amplifier's gain in an AGC loop. | ||