ACVS: Difference between revisions

ACVS (view source)

139 bytes added , 27 April 2018

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 The time to complete the entire refresh cycle is 900 μs.
 The precision of each sample-and-hold voltage 12 bits.
 of the sample-and-hold voltages are used independently.
-Six of the voltages are combined in groups of three, using resistor summing networks,
+The other six voltages are combined in groups of three, using resistor summing networks,
 to produce two outputs that each have 14.6 bit precision.
-These two precision voltages are DLYREF0 and DLYREF1,
+These two precision voltages are DLYREF0 and DLYREF1.
-which are compared with the sweep ramp to generate sweep delay pulse.
+DLYREF0 is the comparator voltage for the SWEEP A delay.
-In earlier analog scopes (e.g., the [[565]]),
+DLYREF1 is the comparator voltage for the SWEEP B delay.
-the precision DC control voltage for the delay ramp comparator
+See schematic below.
+Historic note: In earlier analog scopes (e.g., the [[565]]),
+the basic architecture of the sweep delay is the same,
+but precision DC control voltage for the delay ramp comparator
 was produced by a multi-turn potentiometer on the front panel.