11301

Manuals – Specifications – Links – Pictures

The Tektronix 11301 is a programmable 400 MHz analog oscilloscope that takes up to three 11000-series plug-ins or (vertical) 7000-series plug-ins. Note, however, that the 7000 series plugins have mechanical interlock preventing them from being installed into an 11K mainframe.

The sister model 11302 is basically identical but has a micro-channel plate CRT and 500 MHz bandwidth.

The 11301 has an infrared beam touch screen. There are 10 columns and 14 rows of beams.

The 11301 contains a 77 nanosecond delay line.

Key Specifications

Bandwidth	400 MHz
Sweep	5 ns/Div to 500 ms/Div, 1-2-5, ×10 magnifier (same specs for delayed time base)
Triggering	0.35 Div (int) or 20 mV (ext) to 50 MHz, increasing to 1 Div/150 mV at max. bandwidth
Trigger modes	DC, AC (>50 Hz), HF Reject (< 30 kHz), LF reject (>80 kHz), TV (line or field)
X-Y operation	X from center plugin, bandwidth 3 MHz X-Y phase difference <1° to 1 MHz, <3° to 2 MHz

Internals

The 11301 is an analog oscilloscope that is digitally controlled. Like a typical analog scope, the 11301 has vertical amplifiers, a trigger circuit, a timebase/sweep, a horizontal amplifier, and a CRT. Unlike traditional analog scopes, the 11301 contains a significant amount of digital circuitry, including multiple microprocessors. The digital circuitry provides several externally-observable features:

• self-test and diagnosis
• self-calibration
• remote control via RS-232 or GPIB
• on-screen menu-based touch screen user interface

Digital circuitry also implements some features that were traditionally implemented with analog circuitry, e.g., the trigger holdoff is implemented with a counter instead of with a multivibrator.

There are many DAC-generated analog control voltages in the 11301.

The left and center plug-in can be used as the vertical axis and/or the trigger signal. The right plug-in can used as the horizontal axis and/or the trigger signal.

The RS-232 interface of the 11301 is implemented using an 8251A UART chip, interfaced using an MC1488 line drive and an MC1489 line receiver.

The mainframe communicates with the plug-ins via the Serial Data Interface (SDI). This comprises three signals:

• SDI clock
• SDI mainframe to plug-in
• SDI plug-in to mainframe

On the mainframe side, this communication is controlled by the U1760 SDI chip on the A11 Main Processor board (the top rear board). The 11301 SDI is a synchronous serial interface. The clock signal, which is generated by the mainframe, is 5V TTL, 4 MHz, constantly running.

Pictures

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