6R1A

The Tektronix Type 6R1A is a plug-in for the 567 oscilloscope. It replaced the 6R1. The 6R1A provides digital readout of time and voltage measurements on waveforms. The 6R1A (and the 567 in general) is oriented toward sampling measurements. The 6R1A is a counter and a comparator. To digitize analog voltages, the counter and comparator are used as a ramp-compare ADC. Card Q (Voltmeter) contains a 1MHz crystal oscillator. The counters (Card A) are made of flip-flops made of 2N1754 Germanium PNP transistors.

The 6R1A differs sightly from the 6R1. One difference is the how the 0% zone is determined. In the 6R1, the 0% zone is always the leftmost major division of the trace. The 6R1A allows the 0% zone to be set arbitrarily.

When a 6R1 is used in a 567 with a 3T77, the horizontal sweep signal is generated by the staircase generator circuit in the 3T77 and from R184 in the staircase generator, the sweep signal is sent to the horizontal amplifier circuit of the 3T77, where it enters the sweep mode switch. Assuming that the sweep mode switch is in the NORMAL or SINGLE DISPLAY positions, the sweep signal is sent out through R318 to pin 20 on P22, the connector on the rear of the 3T77. The 567 carries the signal to pin 8 on P32 of the 6R1. Within the 6R1, the sweep signal is carried to pin 7 of the 0% zone card. On the 0% zone card, the sweep signal is buffered by V43, a Nuvistor cathode-follower, and the buffered sweep signal is sent out from pin 10 of the 0% zone card. The primary purpose if the 0% zone circuit is to produce a signal that instructs the memory circuits to sample and hold the voltages at their inputs during the first cm of the sweep. To accomplish this, the 0% zone card compares the sweep voltage with a fixed voltage, putting D43, a 2mA tunnel diode, into the high voltage state whenever the sweep signal is above about 5 V. Since the sweep signal goes from 0 V to 50 V for a complete sweep, 5V corresponds to a point 1 major division from the left edge of the display. The +GATE signal goes high at the beginning of each sweep and returns low at the end of each sweep. The +0% OUT signal is high only during the first cm of the sweep. The logic is +GATE AND NOT (SWEEP > 5V). When the sweep starts, Q23 pulls the top leg of R54 high, and since Q54 is off at the point, the voltage on the bottom leg of R54 also rises, raising the voltage at the base of buffer transistor Q63, which raises the +0% output. When the sweep voltage reaches 5V and the Q54 turns on, the voltage on the bottom leg of R54 drops to near 0 V. The buffer Q63 follows, and the +0% output falls. The -0% output signal is the logical complement of the +0% signal, generated by common-emitter inverter Q64.

6R1 Schematics