7D01: Difference between revisions

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{{Plugin Sidebar 2 |
{{Plugin Sidebar
title=Tektronix 7D01 |
|manufacturer=Tektronix
summary=Logic Analyzer |
|series=7000-series scopes
image=Tek 7D01 Front 2.jpg |  
|type=7D01  
caption=Tektronix 7D01 without display formatter |
|summary=Logic Analyzer  
introduced=1976 |
|image=Tek 7D01 Front 2.jpg  
discontinued=1985 |
|caption=Tektronix 7D01 without display formatter  
series=[[7000-series scopes]]|
|introduced=1976  
manuals=
|discontinued=1985
* [http://w140.com/smb/7d01_sm.pdf Tektronix 7D01 Manual (OCR, PDF)]
|designers=Murlan Kaufman;Keith Taylor;Morris Green;Jeff Bradford;Ed Wolf;Vendell Damm
* [http://w140.com/tekscope_1976vol8no2_7d01.pdf 7D01 Article in 1976 Volume 8 Number 2 Tekscope (PDF)]
|manuals=
* [[Media:070-2205-02.pdf|7D01 Operators Manual]] (OCR)
* [[Media:070-2206-00.pdf|7D01 Instruction Manual 070-2206-00]] (OCR)
* [[Media:070-2206-02.pdf|7D01 Instruction Manual 070-2206-02 Rev. Oct 1982]] (OCR)
* [[Media:Tek_7D01_Anleitung_Deutsch.pdf|Tektronix 7D01 Anleitung]] (Operators Manual, German, OCR)
<small>
'''Alternate copies'''
* [[Media:070-2206-02_2.pdf|7D01 Instruction Manual 070-2206-02 rev. Oct 1982]] (OCR)
 
'''Brochures'''
* [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976]]
</small>
}}
}}
The '''Tektronix 7D01''' is a logic analyzer plug-in for the [[7000-series scopes]]. Compatible extension modules
The '''Tektronix 7D01''' is a 16-channel logic analyzer plug-in for the [[7000-series scopes]] that takes two [[P6451]] 8+1 channel probes.
include the [[DF1]] and [[DF2]] display formatters and the [[DL2]] latch (glitch detector). The 7D01 takes two [[P6451]] 8+1 channel probes.
 
When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
 
When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen [[7603N]].
 
The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier.
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
 
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. 
The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
 
There is no internal glitch detector, but a separate [[DL2]] or [[DL502]] latch plug-in can be used to stretch short pulses ≥5 ns to the clock period.  
The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.
 
Project manager for the 7D01 was [[Murlan Kaufman]].  Project leader was [[Keith Taylor]], with [[Morris Green]] and [[Jeff Bradford]] doing electrical design, and [[Ed Wolf]] mechanical design. [[Vendell Damm]] worked on the active probe.


{{BeginSpecs}}
{{BeginSpecs}}
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* 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)
* 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)
}}
}}
{{Spec | Sampling Rate | 10 ns to 5 ms per sample (1—2—5) or external clock up to 50 MHz}}
{{Spec | Sampling Rate | 10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz}}
{{Spec | Trigger Sources |
{{Spec | Trigger Sources |
* external
* external
Line 28: Line 54:
}}
}}
{{EndSpecs}}
{{EndSpecs}}
==Internals==
The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs. 
The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.
The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails.
There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable.  ''(Any known uses?)''


==Notes==
==Notes==
Line 33: Line 67:


''When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.''
''When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.''
The 7D01 is often affected by [[bad TI IC sockets]], see [[7D01/Repairs|the Repairs tab]].


==Links==
==Links==
 
* [[Media:Tekscope_1976_V8_N2.pdf|Tekscope Volume 8 Number 2, 1976, p.2+ – Keith Taylor, ''A 16-channel logic analyzer for the 7000 Series'']]
* [http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/logicanalyzer_7D01.htm 7D01 @ amplifier.cd]
* [https://paulcarbone.com/blog/tekronix-7d01-logic-analyzer/ 7D01 @ paulcarbone.com] (with detailed photos)
* [http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/logicanalyzer_7D01.htm 7D01 @ amplifier.cd]
* [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com]
* [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com]


Line 45: Line 82:
Tek 7d01 and df1 in 7313.jpg|7D01 and [[DF1]] in [[7313]]
Tek 7d01 and df1 in 7313.jpg|7D01 and [[DF1]] in [[7313]]
Tek df2 7d01 lit.jpg
Tek df2 7d01 lit.jpg
Tek 7D01 DF1.jpg          | 7D01+[[DF1]] Front
Tek_7D01_Front.jpg        | 7D01+[[DF1]] Front
Tek_7D01_Front.jpg        | 7D01+[[DF1]] Front
Tek_7D01_Left.jpg        | 7D01 Left
Tek_7D01_Left.jpg        | 7D01 Left
Line 50: Line 88:
Tek_7D01_Bottom.jpg      | 7D01 Bottom
Tek_7D01_Bottom.jpg      | 7D01 Bottom
Tek_7D01_rear.jpg        | 7D01 Rear (back plate removed)
Tek_7D01_rear.jpg        | 7D01 Rear (back plate removed)
7d01-df1-front.jpg
7d01-df1-top.jpg
7d01-df1-bottom.jpg
Tek_7D01_Cursor.jpg      | 7D01 Cursor Board
Tek_7D01_Cursor.jpg      | 7D01 Cursor Board
Tek_7D01_Memory.jpg      | 7D01 Memory Board
Tek_7D01_Memory.jpg      | 7D01 Memory Board
Tek_7D01_timing.jpg      | 7D01 Timing Diagram
Tek_7D01_timing.jpg      | Standalone 7D01 Timing Diagram (using mainframe readout)
Tek_7D01-DF01_timing.jpg  | 7D01 + [[DF1]] Timing Diagram
Tek_7D01-DF01_timing.jpg  | 7D01 + [[DF1]]/DF2 Timing Diagram (readout from DF)
Tek_7D01-DF01_table.jpg  | 7D01 + [[DF1]] State Table
Tek_7D01-DF01_table.jpg  | 7D01 + [[DF1]]/DF2 State Table
</gallery>
</gallery>
{{Custom ICs|7D01}}


[[Category:7000 series special-function plugins]]
[[Category:7000 series special-function plugins]]
[[Category:Logic Analyzers]]
[[Category:Logic analyzers]]

Revision as of 06:54, 13 July 2022

Tektronix 7D01
Logic Analyzer
Tektronix 7D01 without display formatter

Compatible with 7000-series scopes

Produced from 1976 to 1985

Manuals
Manuals – Specifications – Links – Pictures

The Tektronix 7D01 is a 16-channel logic analyzer plug-in for the 7000-series scopes that takes two P6451 8+1 channel probes.

When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's readout system to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).

When combined with an optional DF1 or DF2 display formatter (attached to the left of the 7D01 through a DD-50 connector), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen 7603N.

The 9th channel on the first probe serves as an external clock input, that on the second probe as an external qualifier. The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.

The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock. A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.

There is no internal glitch detector, but a separate DL2 or DL502 latch plug-in can be used to stretch short pulses ≥5 ns to the clock period. The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.

Project manager for the 7D01 was Murlan Kaufman. Project leader was Keith Taylor, with Morris Green and Jeff Bradford doing electrical design, and Ed Wolf mechanical design. Vendell Damm worked on the active probe.

Key Specifications

Channels
  • 4 channels at 1016 bits/channel, maximum external clock period 10 ns (100 MHz)
  • 8 channels at 508 bits/channel, maximum external clock period 20 ns (50 MHz)
  • 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)
Sampling Rate 10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz
Trigger Sources
  • external
  • channel 0 data
  • 16 channel word recognizer
  • manual

Internals

The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs. The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.

The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails.

There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable. (Any known uses?)

Notes

Note about external clock rates (from Jim Mauck):

When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.

The 7D01 is often affected by bad TI IC sockets, see the Repairs tab.

Links

Pictures

Custom ICs used in the 7D01

Page Model Part nos Description Designers Used in
155-0090-00 M059 155-0090-00 155-0090-01 155-0090-02 four-decade counter, latch and D/A converter Mike Metcalf 7B85 7D01 7D12 7D15 7J20
155-0171-00 M150A 155-0171-00 four-decade counter, latch and D/A converter Mike Metcalf 7B85 7D01 7D12 7D15 7J20