When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's readout system to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
When combined with an optional DF1 or DF2 display formatter (attached to the left of the 7D01 through a DD-50 connector), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen 7603N.
The 9th channel on the first probe serves as an external clock input, that on the second probe as an external qualifier. The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock. A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
There is no internal glitch detector, but a separate DL2 or DL502 latch plug-in can be used to stretch short pulses ≥5 ns to the clock period. The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.
Project manager for the 7D01 was Murlan Kaufman. Project leader was Keith Taylor, with Morris Green and Jeff Bradford doing electrical design, and Ed Wolf mechanical design. Wendell Damm worked on the active probe.
|Sampling Rate||10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz|
The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs. The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.
The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails.
There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable. (Any known uses?)
Note about external clock rates (from Jim Mauck):
When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.
- Tekscope Volume 8 Number 2, 1976, p.2+ – Keith Taylor, A 16-channel logic analyzer for the 7000 Series
- 7D01 @ paulcarbone.com (with detailed photos)
- 7D01 @ amplifier.cd
- 7D01 @ barrytech.com
7D01 in 7704A mainframe
7D01 Rear (back plate removed)
7D01 Cursor Board
7D01 Memory Board
Standalone 7D01 Timing Diagram (using mainframe readout)
7D01 + DF1/DF2 Timing Diagram (readout from DF)
7D01 + DF1/DF2 State Table
Some Parts Used in the 7D01
|Part||Part Number(s)||Class||Description||Used in|
|155-0090-00||155-0090-00 • 155-0090-01 • 155-0090-02||Monolithic integrated circuit||four-decade counter||7B85 • 7D01 • 7D12 • 7D15 • 7J20|
|155-0171-00||155-0171-00||Monolithic integrated circuit||4-decade counter, latch and D/A converter||7B85 • 7D01 • 7D12 • 7D15 • 7J20|