7D14: Difference between revisions
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{{Plugin Sidebar| | {{Plugin Sidebar 2| | ||
title=Tektronix 7D14| | title=Tektronix 7D14| | ||
summary=525 MHz frequency counter| | summary=525 MHz frequency counter| | ||
image= | image=7d14-front.jpg | | ||
caption=7D14 front view | caption=7D14 front view | | ||
introduced=1971 | | |||
discontinued=1980 | | |||
series=[[7000-series scopes]]| | series=[[7000-series scopes]]| | ||
manuals= | manuals= | ||
* [ | * [[Media:070-1097-00.pdf|Tektronix 7D14 Service]] (OCR, PDF) | ||
* [[Media:7000 Series Digital Plug-In Applications.pdf|7000 Series Digital Plug-In Applications (PDF)]] | |||
}} | }} | ||
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In a vertical compartment, the trigger signal (i.e. the "shaped" input) can be displayed as the module's Y output. | In a vertical compartment, the trigger signal (i.e. the "shaped" input) can be displayed as the module's Y output. | ||
{{BeginSpecs}} | {{BeginSpecs}} | ||
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}} | }} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
==Internals== | |||
An input section using relays selects the counter signal from the internal trigger path or external input, and activates 50 Ω termination and/or attenuators. | |||
A differential FET buffer + bipolar amplifier stage drives a counter gate that uses a 10 mA [[tunnel diode]] as the switching element. | |||
The first decade is implemented as a divide-by-2 ECL flip-flop ([[156-0377-00]]) followed by a 5-stage ring counter made with discrete transistor pairs (note circular layout) and some logic to BCD-encode the count result. | |||
The following seven counter stages are conventional TTL decade ripple counters (N8292A). | |||
The counter outputs are multiplexed onto a common 4-bit bus using open-collector NAND gates under control of the mainframe's [[7000 series readout system|readout system]]. The multiplexed digit value feeds a D/A converter (Tek [[155-0038-01]]) that in turn drives the analog row and column returns to the readout system. A separate blanking logic eliminates leading zeroes and displays a ">" sign in the leftmost column if the counter overflows. | |||
==Links== | ==Links== | ||
* [http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/7D14.htm 7D14 page @ amplifier.cd] | * [http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/7D14.htm 7D14 page @ amplifier.cd] | ||
* [http://www.barrytech.com/tektronix/tek7000/tek7d14.html 7D14 page @ barrytech.com] | |||
==Prices== | |||
{| class="wikitable" | |||
|- | |||
!Year | |||
! 1973 | |||
! 1976 | |||
! 1980 | |||
|- | |||
!Price | |||
| align="right" | $1,400 | |||
| align="right" | $1,550 | |||
| align="right" | $2,075 | |||
|- | |||
!2015 value | |||
| align="right" | $7,450 | |||
| align="right" | $6,430 | |||
| align="right" | $5,950 | |||
|- | |||
|} | |||
==Pictures== | ==Pictures== | ||
[[ | <gallery> | ||
File:7d14-front.jpg | 7D14 front panel. The unit pictured was able to count up to 640 MHz on the external input and 532 MHz on the trigger path (7A19 in 7904). | |||
File:7d14-left.jpg | 7D14 left side | |||
File:7d14-right.jpg | 7D14 right side | |||
File:7d14-input-amp.jpg | 7D14 detail - input amplifier | |||
File:7d14-gate.jpg | 7D14 detail - counter gate | |||
File:7d14-div2.jpg | 7D14 detail - 525 MHz divide-by-2 stage | |||
File:7d14-div5.jpg | 7D14 detail - divide-by-5 discrete ring counter stage | |||
File:7d14-screen.jpg | 7D14 screen picture - 500 MHz signal counted on trigger path ([[7A19]] amplifier, [[7B92A]] time base in a [[7904]] mainframe) | |||
File:Tek 7d14 1.jpg | |||
File:Tek 7d14 2.jpg | |||
File:Tek 7d14 3.jpg | |||
</gallery> | |||
[[Category:Frequency counters]] | [[Category:Frequency counters]] | ||
[[Category:7000 series special-function plugins]] | [[Category:7000 series special-function plugins]] |
Revision as of 07:07, 24 January 2021
The Tektronix 7D14 is a 525 MHz frequency counter plug-in for 7000 series mainframes.
It uses the mainframe's readout system to display an eight-digit count on the CRT. Modes include frequency, frequency ratio and events count using manual or external gate.
When installed in a horizontal compartment, it can count the trigger pickoff from a vertical amplifier unit. This allows simultaneous viewing and counting of a signal in four-bay mainframes.
In a vertical compartment, the trigger signal (i.e. the "shaped" input) can be displayed as the module's Y output.
Key Specifications
Frequency | 525 MHz (5 MHz bandwidth limiting switch available) |
---|---|
Sensitivity | 100 mV to 10 V |
Input Impedance | 50 Ω or 1 MΩ // 20 pF on external input, 1.5 Div internal when set to "Trig Source" |
Gate time | 1 ms to 10 s |
Display time | 0.1 s to 5 s or infinite |
Features |
|
Internals
An input section using relays selects the counter signal from the internal trigger path or external input, and activates 50 Ω termination and/or attenuators.
A differential FET buffer + bipolar amplifier stage drives a counter gate that uses a 10 mA tunnel diode as the switching element.
The first decade is implemented as a divide-by-2 ECL flip-flop (156-0377-00) followed by a 5-stage ring counter made with discrete transistor pairs (note circular layout) and some logic to BCD-encode the count result.
The following seven counter stages are conventional TTL decade ripple counters (N8292A).
The counter outputs are multiplexed onto a common 4-bit bus using open-collector NAND gates under control of the mainframe's readout system. The multiplexed digit value feeds a D/A converter (Tek 155-0038-01) that in turn drives the analog row and column returns to the readout system. A separate blanking logic eliminates leading zeroes and displays a ">" sign in the leftmost column if the counter overflows.
Links
Prices
Year | 1973 | 1976 | 1980 |
---|---|---|---|
Price | $1,400 | $1,550 | $2,075 |
2015 value | $7,450 | $6,430 | $5,950 |
Pictures
-
7D14 front panel. The unit pictured was able to count up to 640 MHz on the external input and 532 MHz on the trigger path (7A19 in 7904).
-
7D14 left side
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7D14 right side
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7D14 detail - input amplifier
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7D14 detail - counter gate
-
7D14 detail - 525 MHz divide-by-2 stage
-
7D14 detail - divide-by-5 discrete ring counter stage
-
-
-