ACVS: Difference between revisions

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A refresh cycle sequentially refreshes the voltage on each of the sample-and-hold capacitors.
A refresh cycle sequentially refreshes the voltage on each of the sample-and-hold capacitors.
The time to complete the entire refresh cycle is 900 μs.
The time to complete the entire refresh cycle is 900 μs.
The precision is 12 bits for all but two of the analog outputs.
On those two, the precisions is 14.6 bits.
These high-precision outputs are formed by combining three 12-bit outputs using resistor summing networks.

Revision as of 18:46, 26 April 2018

Tektronix 11000-series plug-ins and mainframes contain a subsystem called the Analog Control Voltage System (ACVS). The ACVS produces several independently controllable DC voltages. The voltages are fed to the analog signal path circuitry (e.g., the OFFSET input of the M377, or the OFFSET pin on the TekProbe input connector. The number of voltages produced by the ACVS depends on how many channels the plug-in has. For example, the 11A34, which has four channels, has an ACVS that produces sixteen control voltages.

AVCS in 11000-Series Plug-ins

The ACVS comprises three parts:

  • AD667 12-bit DAC (single output)
  • CD4051 analog switches and holding capacitors, implementing a set of sample and hold circuits
  • TL074 JFET-input opamps, providing a set of unity-gain output buffers

The output from the DAC is sampled and held, and the buffered voltages are fed to the rest of the plug-in. The voltages in the sample and hold are periodically refreshed. The sample and hold and output buffers are on a daughterboard. (See photo below)

The ACVS is controlled by the M382 chip, which also implements SDI and sequences the amplifier output enable signals.

ACVS in 11000-Series Mainframes

In the 11300 mainframes, the ACVS is controlled by an 8051-family microcontroller. It employs a DAC312 12-bit DAC, whose output is fed to an array of 28 sample-and-hold circuits similar to the ones in the plug-ins. A refresh cycle sequentially refreshes the voltage on each of the sample-and-hold capacitors. The time to complete the entire refresh cycle is 900 μs. The precision is 12 bits for all but two of the analog outputs. On those two, the precisions is 14.6 bits. These high-precision outputs are formed by combining three 12-bit outputs using resistor summing networks.