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ACVS: Difference between revisions
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The ACVS is controlled by the [[M382]] chip, which also implements [[SDI|Serial Data Interface (SDI)]] | The ACVS is controlled by the [[M382]] chip, which also implements [[SDI|Serial Data Interface (SDI)]] | ||
and sequences the amplifier output enable signals. | and sequences the amplifier output enable signals. | ||
The ACVS also has a loopback function using one of the 74HC4051 analog multiplexers. | |||
The output voltages can be routed to a TLC540 8-bit ADC in the plug-in (U750 in the 11A52) | |||
which allows the microprocessor to verify that the control voltages are approximately correct. | |||
<gallery> | <gallery> | ||
Tek 11a32 sample and hold.jpg|ACVS sample-and-hold circuits on daughterboard on [[11A32]] | Tek 11a32 sample and hold.jpg|ACVS sample-and-hold circuits on daughterboard on [[11A32]] | ||
Tektronix 11A52 main amp & control schematic.JPG|ACVS sample and hold schematic in the [[11A52]] | Tektronix 11A52 main amp & control schematic.JPG|ACVS sample and hold schematic in the [[11A52]] | ||
Tek 11a33 670-8986 crop.jpg|ACVS in 11A33 | |||
670-8986-00 Sample and Hold Farm-11K plugins.jpg|670-8986-00 Sample and Hold Farm with Labeled Components | |||
</gallery> | </gallery> | ||
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The precision of each sample-and-hold voltage 12 bits. | The precision of each sample-and-hold voltage 12 bits. | ||
Twenty six of the sample-and-hold voltages are used independently. | |||
The other six voltages are combined in groups of three | The other six voltages are combined in groups of three using resistor summing networks | ||
to produce two outputs that each have 14.6 bit precision. | to produce two outputs that each have 14.6 bit precision. | ||
These two precision voltages are DLYREF0 and DLYREF1. | These two precision voltages are DLYREF0 and DLYREF1. | ||
| Line 40: | Line 47: | ||
DLYREF1 is the comparator voltage for the SWEEP B delay. | DLYREF1 is the comparator voltage for the SWEEP B delay. | ||
See schematic below. | See schematic below. | ||
Historical note: | Historical note: Earlier analog scopes (e.g., the [[565]]) | ||
the basic architecture | used the same basic architecture for sweep delay: | ||
the instantaneous sweep ramp voltage is compared with | |||
a user-controllable DC voltage that represents the desired amount of delay. | |||
In 11300 scopes, the DC voltage is produced by the ACVS; | |||
In the 565 it is produced by a multi-turn potentiometer on the front panel. | |||
The ACVS in DSA600 mainframes generates 48 control voltages. | |||
<gallery> | <gallery> | ||
Tek 11300 acvs.png|ACVS schematic in 11300 mainframes | Tek 11300 acvs.png|ACVS schematic in 11300 mainframes. | ||
Tek 11300 dlyref3.png|The weighted sum of three ACVS voltages is fed to the delay ramp comparator | Tek 11300 dlyref3.png|The weighted sum of three ACVS voltages is fed to the delay ramp comparator. | ||
Tek_565_delay_pickoff.png|Delayed trigger in 565. Delay Interval potentiometer produces control voltage. | |||
</gallery> | </gallery> | ||
[[Category:Circuits and Concepts]] | [[Category:Circuits and Concepts]] | ||