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|series=7D01
|series=7D01
|type=DF1
|type=DF1
|summary=Display Formatter
|summary=display formatter
|image=Tek df1 front.JPG
|image=Tek df1 front.JPG
|caption=DF1 front panel
|caption=DF1 front panel
|introduced=1977
|introduced=1976
|discontinued=1985
|discontinued=1985
|designers=Murlan Kaufman;Dave Lowry;Jeff Bradford;Ed Wolf
|manuals=
|manuals=
'''DF1'''
'''DF1'''
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* [[Media:070-2478-00.pdf|Tektronix DF2 Manual]] (OCR)  
* [[Media:070-2478-00.pdf|Tektronix DF2 Manual]] (OCR)  
* [[Media:Tek_DF1_DF2_Anleitung_Deutsch.pdf|Tektronix DF1/DF2 Anleitung]] (Operators Manual, German, OCR)
* [[Media:Tek_DF1_DF2_Anleitung_Deutsch.pdf|Tektronix DF1/DF2 Anleitung]] (Operators Manual, German, OCR)
<small>
'''Alternate copies'''
* [http://w140.com/smb/df1_sm.pdf Tektronix DF1 Manual] (OCR)
</small>


{{ROM Images}}
{{ROM Images}}
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* U820: [[Media:156-1132-00.bin|156-1132-00]] (2k×8, [[6831B]], DF2 only)
* U820: [[Media:156-1132-00.bin|156-1132-00]] (2k×8, [[6831B]], DF2 only)
}}
}}
The '''Tektronix DF1''', [[introduced in 1977]], is a "display formatter" for use with the [[7D01]] logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared.  The DF1 was [[introduced in 1977]].
The '''Tektronix DF1''', [[introduced in 1977]], is a "display formatter" for use with the [[7D01|7D01 logic analyzer]]. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared.  The DF1 was [[introduced in 1977]].


The '''Tektronix DF2''', [[introduced in 1978]], is the same as the DF1 with the exception of an added front-panel "Menu" key and an additional ROM (on a daughter board) that supports GPIB and ASCII modes.   
The '''Tektronix DF2''', [[introduced in 1978]], is the same as the DF1 with the exception of an added front-panel "Menu" key and an additional ROM (on a daughter board) that supports GPIB and ASCII modes.   


The DF2 does not have a GPIB interface, it can only analyze external GPIB traffic.  For this purpose, a [[103-0209-00|103-0209-00 GPIB to probe comb adapter]] was supplied with the DF2.  This connects GPIB DIO1..DIO8 to CH8..CH15, DAV to the CLOCK input, ATN to CH7, EOI to CH6, SRQ to CH5, and REN to CH4.  GPIB signals DAV, NRFD, NDAC and IFC brought out to pins on the connector.  CH3..0 are user defined inputs that can track any of these signals, or others as needed.  For GPIB analysis, bus data is acquired synchronously using the negative-going edge of the GPIB DAV (Data Valid) line as an external clock.
The DF2 does not have a GPIB interface, it can only analyze external GPIB traffic.  For this purpose, a [[103-0209-00|103-0209-00 GPIB to probe comb adapter]] was supplied with the DF2, which connects GPIB DIO1..DIO8 to CH8..CH15, DAV to the CLOCK input, ATN to CH7, EOI to CH6, SRQ to CH5, and REN to CH4.  GPIB signals DAV, NRFD, NDAC and IFC brought out to pins on the connector.  CH3..0 are user defined inputs that can track any of these signals, or others as needed.  For GPIB analysis, bus data is acquired synchronously using the negative-going edge of the GPIB DAV (Data Valid) line as an external clock.


Project manager for the DF1/DF2 was [[Murlan Kaufman]].
From TekScope V.8 N.4 1976:
<blockquote>
Project manager for the DF1/DF2 was [[Murlan Kaufman]], with [[Dave Lowry]] and [[Jeff Bradford]] doing the electrical and software design, and [[Ed Wolfe]] doing mechanical design.
[[Roy Kaufman]] and [[Joe Gaudio]], Evaluation Engineers, and [[Dave McCullough]], Marketing Program Manager, also made valuable contributions.
Special thanks are due to [[Jack Lyngdal]] and [[Nick Colvin]], Manufacturing; [[Betty Spohn]], ECB; [[Jan Bowden]], Prototypes; and to everyone else who contributed to a a speedy, efficient completion of the project.
</blockquote>


{{BeginSpecs}}
{{BeginSpecs}}
{{Spec | Memory | One reference table memory, 1kB, same as 7D01 capacity (max. 16 channels at 254 bits/ch), plus 1kB display RAM }}
{{Spec | Memory | One reference table memory, 1kB, same as 7D01 capacity (max. 16 channels at 254 bits/ch), plus 1kB display RAM }}
{{Spec | Display modes |
{{Spec | Display modes |
'''7D01/7D02'''
'''7D01/DF1 or DF2'''
* Timing: Standard 7D01 display – 4, 8 or 16 bits
* Timing: Standard 7D01 display – 4, 8 or 16 bits
* State table: Hexadecimal, octal, or binary formats; two tables (reference, 7D01 memory) of 17 lines of 16-bit words
* State table: Hexadecimal, octal, or binary formats; two tables (reference, 7D01 memory) of 17 lines of 16-bit words
* Map: Dot display of the 16 data channels in X-Y coordinate points. Each dot location represents one possible combination of up to 16 inputs to the 7D01.
* Map: Dot display of the 16 data channels in X-Y coordinate points. Each dot location represents one possible combination of up to 16 inputs to the 7D01.
'''7D02 only'''
'''7D01/DF2'''
* GPIB: Displays 17 lines of decoded GPIB operations and/or ASCII data, and up to four user-defined input signal states.
* GPIB: Displays 17 lines of decoded GPIB operations and/or ASCII data, and up to four user-defined input signal states.
* ASCII: Displays 17 lines of decoded ASCII character along with its binary, octal, or hex value, in either 8– or 16–bit modes.
* ASCII: Displays 17 lines of decoded ASCII character along with its binary, octal, or hex value, in either 8– or 16–bit modes.
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{{Spec | Reset output | Positive 100 μs pulse, ≤0.4 V / ≥2.4 V }}
{{Spec | Reset output | Positive 100 μs pulse, ≤0.4 V / ≥2.4 V }}
{{EndSpecs}}
{{EndSpecs}}
==Links==
{{Documents|Link=DF1}}


==Internals==
==Internals==
An internal jumper allows the user to select the source of the on-screen readout in timing diagram mode, which can be either the mainframe readout supplied by the 7D01, or superimposed by the DF1/DF2.  The latter is the standard setting and allows the DF1/DF2+7D01 combination to be used in mainframes without readout, e.g. the large-screen [[7603N]].
An internal jumper allows the user to select the source of the on-screen readout in timing diagram mode, which can be either the mainframe readout supplied by the 7D01, or superimposed by the DF1/DF2.  The latter is the standard setting and allows the DF1/DF2+7D01 combination to be used in mainframes without readout, e.g. the large-screen [[7603N]].


The DF1/DF2 has no direct connection to the scope mainframe, it attaches to the 7D01 through a 50-pin [[D-sub connector]] on the right side panel only.  The DF1/DF2 and 7D01 are mechanically coupled by three nylon standoffs that slide into cutouts in the 7D01's case rails. The bottom two standoffs are fixed and are inserted first, then the connector is plugged in and the third, sliding, stand-off at the top is moved to its locked position.
The DF1/DF2 has no direct connection to the scope mainframe − it attaches to the 7D01 through a 50-pin [[D-sub connector]] on the right side panel only.  The DF1/DF2 and 7D01 are mechanically coupled by three nylon standoffs that slide into cutouts in the 7D01's case rails. The bottom two standoffs are fixed and are inserted first, then the connector is plugged in and the third, sliding, stand-off at the top is moved to its locked position.


The DF1/DF2 is built around a [[Motorola 6800]] microprocessor with two (DF2: three) 2K×8 masked ROMs and sixteen 1K×1 SRAMs ([[Intel 2102]]).  
The DF1/DF2 is built around a [[Motorola 6800]] microprocessor with two (DF2: three) 2K×8 masked ROMs and sixteen 1K×1 SRAMs ([[Intel 2102]]).  


The DF1, DF2 and 7D01 are often affected by [[bad TI IC sockets]], see [[7D01/Repairs|the Repairs tab]].
The DF1, DF2 and 7D01 are often affected by [[bad TI IC sockets]] and/or ROM failures, see [[7D01/Repairs|the Repairs tab]].


===Memory map===
===Memory map===
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|}
|}
</small>
</small>
==Links==
* Dave Lowry, Jeff Bradford: ''A display formatter — the indispensable tool for the data domain.'' In [[Media:Tekscope_1976_V8_N4_with_Supplement.pdf|TekScope Vol. 8 No. 4, Winter 1976]]
==Pictures==
==Pictures==


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Tek DF1 right 0670-4661-01.jpg                  | DF1 internal, right side
Tek DF1 right 0670-4661-01.jpg                  | DF1 internal, right side
Tek DF1 left 0670-4662-00 with ROMs removed.jpg | DF1 internal, left side, ROM chips removed from sockets
Tek DF1 left 0670-4662-00 with ROMs removed.jpg | DF1 internal, left side, ROM chips removed from sockets
Tek DF1 left with ROM adapter.jpg              | DF1 internal, left side, with ROM replacement piggyback board
Tek DF1 left with ROM adapter.jpg              | DF1 internal, left side, with [[7D01/Repairs|ROM replacement piggyback board]] (prototype)
Tek DF1 keyboard PCB.jpg                        | DF1 front with faceplate removed, showing keyboard PCB
Tek DF1 ROM piggyback PCB.jpg                  | [[7D01/Repairs|ROM replacement piggyback board]] (production)
Tek DF1 keyboard PCB.jpg                        | DF1 front with faceplate removed, showing keyboard PCB. Note three unpopulated key positions.


Tek df1 internal right.jpg
Tek df1 internal right.jpg
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===Displays===
===Displays===
<gallery>
<gallery>
DF2 display 01.jpg | Timing diagram with mainframe readout
DF2 display 09.jpg | Timing diagram with DF readout
DF2 display 08.jpg | Timing diagram zoomed
DF2 display 02.jpg | Map diagram with octal cursor-position readout
DF2 display 07.jpg | Map diagram with binary cursor-position readout
DF2 display 03.jpg | Octal state table without reference
DF2 display 04.jpg | Binary state table with reference
DF2 display 05.jpg | DF2 GPIB table (random data)
DF2 display 06.jpg | DF2 ASCII table (16 bit mode in 2 columns). Note lowercase character "o" is displayed as <O>.
Tek_7D01-DF01_timing.jpg  | 7D01 + DF1/DF2 Timing Diagram (with DF1/DF2 readout)
Tek_7D01-DF01_timing.jpg  | 7D01 + DF1/DF2 Timing Diagram (with DF1/DF2 readout)
Tek_7D01-DF01_table.jpg    | 7D01 + DF1/DF2 State Table example - 8 bit mode, 7D01 table left with highlighted differences to DF1/DF2 reference table on the right
Tek_7D01-DF01_table.jpg    | 7D01 + DF1/DF2 State Table example - 8 bit mode, 7D01 table left with highlighted differences to DF1/DF2 reference table on the right
</gallery>
</gallery>


==Components==
{{Parts|DF1}}
{{Parts|DF2}}


[[Category:7000 series special-function plugins]]
[[Category:7000 series special-function plugins]]
[[Category:Logic analyzers]]
[[Category:Logic analyzers]]

Latest revision as of 07:36, 6 December 2023

Tektronix DF1
display formatter
DF1 front panel

Compatible with 7D01

Produced from 1976 to 1985

Manuals
ROM Images
(All manuals in PDF format unless noted otherwise)
Manuals – Specifications – Links – Pictures

The Tektronix DF1, introduced in 1977, is a "display formatter" for use with the 7D01 logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared. The DF1 was introduced in 1977.

The Tektronix DF2, introduced in 1978, is the same as the DF1 with the exception of an added front-panel "Menu" key and an additional ROM (on a daughter board) that supports GPIB and ASCII modes.

The DF2 does not have a GPIB interface, it can only analyze external GPIB traffic. For this purpose, a 103-0209-00 GPIB to probe comb adapter was supplied with the DF2, which connects GPIB DIO1..DIO8 to CH8..CH15, DAV to the CLOCK input, ATN to CH7, EOI to CH6, SRQ to CH5, and REN to CH4. GPIB signals DAV, NRFD, NDAC and IFC brought out to pins on the connector. CH3..0 are user defined inputs that can track any of these signals, or others as needed. For GPIB analysis, bus data is acquired synchronously using the negative-going edge of the GPIB DAV (Data Valid) line as an external clock.

From TekScope V.8 N.4 1976:

Project manager for the DF1/DF2 was Murlan Kaufman, with Dave Lowry and Jeff Bradford doing the electrical and software design, and Ed Wolfe doing mechanical design. Roy Kaufman and Joe Gaudio, Evaluation Engineers, and Dave McCullough, Marketing Program Manager, also made valuable contributions. Special thanks are due to Jack Lyngdal and Nick Colvin, Manufacturing; Betty Spohn, ECB; Jan Bowden, Prototypes; and to everyone else who contributed to a a speedy, efficient completion of the project.

Key Specifications

Memory One reference table memory, 1kB, same as 7D01 capacity (max. 16 channels at 254 bits/ch), plus 1kB display RAM
Display modes

7D01/DF1 or DF2

  • Timing: Standard 7D01 display – 4, 8 or 16 bits
  • State table: Hexadecimal, octal, or binary formats; two tables (reference, 7D01 memory) of 17 lines of 16-bit words
  • Map: Dot display of the 16 data channels in X-Y coordinate points. Each dot location represents one possible combination of up to 16 inputs to the 7D01.

7D01/DF2

  • GPIB: Displays 17 lines of decoded GPIB operations and/or ASCII data, and up to four user-defined input signal states.
  • ASCII: Displays 17 lines of decoded ASCII character along with its binary, octal, or hex value, in either 8– or 16–bit modes.
Reset output Positive 100 μs pulse, ≤0.4 V / ≥2.4 V

Links

Documents Referencing DF1

Document Class Title Authors Year Links
Tekscope 1976 V8 N4 with Supplement.pdf Article A Display Formatter – The Indispensable Tool for the Data Domain Dave Lowry • Jeff Bradford 1976 DF1 • 7D01
AX-3524.pdf Application Note Troubleshooting a Microprocessor (Logic Analyzer App Note #57K1.0) 1977 7D01 • DF1

Internals

An internal jumper allows the user to select the source of the on-screen readout in timing diagram mode, which can be either the mainframe readout supplied by the 7D01, or superimposed by the DF1/DF2. The latter is the standard setting and allows the DF1/DF2+7D01 combination to be used in mainframes without readout, e.g. the large-screen 7603N.

The DF1/DF2 has no direct connection to the scope mainframe − it attaches to the 7D01 through a 50-pin D-sub connector on the right side panel only. The DF1/DF2 and 7D01 are mechanically coupled by three nylon standoffs that slide into cutouts in the 7D01's case rails. The bottom two standoffs are fixed and are inserted first, then the connector is plugged in and the third, sliding, stand-off at the top is moved to its locked position.

The DF1/DF2 is built around a Motorola 6800 microprocessor with two (DF2: three) 2K×8 masked ROMs and sixteen 1K×1 SRAMs (Intel 2102).

The DF1, DF2 and 7D01 are often affected by bad TI IC sockets and/or ROM failures, see the Repairs tab.

Memory map

Address (hex) Use
0000-007F Scratchpad RAM (U274, Motorola 6810A)
0080-00FF I/O registers
4000-47FF ROM U820 on DF2 expansion board (156-1132-00, 2k×8, 6831B)
4800-4FFF ROM socket on DF2 expansion board, unused
5000-57FF ROM socket on DF2 expansion board, unused
5800-5FFF ROM socket on DF2 expansion board, unused
6000-63FF 1k RAM
8000-63FF 1k display RAM, "write-only"
Axxx Vertical map address register (→ U552, U554)
Cxxx Horizontal map address register (→ U452, U454)
F000-F7FF ROM U294 (156-0900-00, 2k×8, GI RO-3-8316 or Mostek MK31000)
F800-FFFF ROM U284 (156-0899-00, 2k×8, GI RO-3-8316 or Mostek MK31000)

Links

Pictures

DF1

DF2

  • DF2 front panel

    DF2 front panel

Displays

  • Timing diagram with mainframe readout

    Timing diagram with mainframe readout

  • Timing diagram with DF readout

    Timing diagram with DF readout

  • Timing diagram zoomed

    Timing diagram zoomed

  • Map diagram with octal cursor-position readout

    Map diagram with octal cursor-position readout

  • Map diagram with binary cursor-position readout

    Map diagram with binary cursor-position readout

  • Octal state table without reference

    Octal state table without reference

  • Binary state table with reference

    Binary state table with reference

  • DF2 GPIB table (random data)

    DF2 GPIB table (random data)

  • DF2 ASCII table (16 bit mode in 2 columns). Note lowercase character "o" is displayed as <O>.

    DF2 ASCII table (16 bit mode in 2 columns). Note lowercase character "o" is displayed as <O>.

  • 7D01 + DF1/DF2 Timing Diagram (with DF1/DF2 readout)

    7D01 + DF1/DF2 Timing Diagram (with DF1/DF2 readout)

  • 7D01 + DF1/DF2 State Table example - 8 bit mode, 7D01 table left with highlighted differences to DF1/DF2 reference table on the right

    7D01 + DF1/DF2 State Table example - 8 bit mode, 7D01 table left with highlighted differences to DF1/DF2 reference table on the right

Components

Some Parts Used in the DF1

Part Part Number(s) Class Description Used in
Intel 2102 156-0291-00 Monolithic integrated circuit 1k×1 static RAM 833 • DF1 • DF2 • P7001 • Nicolet 526
MC1408 156-0509-00 Monolithic integrated circuit 8-bit multiplying DAC DF1 • 7B81P
Mostek MK31000 Monolithic integrated circuit 2k×8 mask-programmable ROM DF1 • DF2
Motorola 6800 156-0426-00 Monolithic integrated circuit 8-bit microprocessor 021-0206-00 • 021-0374-00 • 067-0902-00 • 067-1137-99 • 222 • 222A • 222PS • 2424L • 2445 • 2465 • 4051 • 7912 • 7912AD • 7A16P • 7A29P • 7B81P • 7B90P • 833 • 834 • CG5001 • CG551AP • CG5010 • CG5011 • DF1 • DF2 • DM5010 • MI5010 • SI5010 • PS5004 • PS5010 • SG5010
Motorola 6810 156-0716-00 Monolithic integrated circuit 128×8-bit static RAM 021-0206-00 • DF1 • DF2


Some Parts Used in the DF2

Part Part Number(s) Class Description Used in
Intel 2102 156-0291-00 Monolithic integrated circuit 1k×1 static RAM 833 • DF1 • DF2 • P7001 • Nicolet 526
Mostek MK31000 Monolithic integrated circuit 2k×8 mask-programmable ROM DF1 • DF2
Motorola 6800 156-0426-00 Monolithic integrated circuit 8-bit microprocessor 021-0206-00 • 021-0374-00 • 067-0902-00 • 067-1137-99 • 222 • 222A • 222PS • 2424L • 2445 • 2465 • 4051 • 7912 • 7912AD • 7A16P • 7A29P • 7B81P • 7B90P • 833 • 834 • CG5001 • CG551AP • CG5010 • CG5011 • DF1 • DF2 • DM5010 • MI5010 • SI5010 • PS5004 • PS5010 • SG5010
Motorola 6810 156-0716-00 Monolithic integrated circuit 128×8-bit static RAM 021-0206-00 • DF1 • DF2
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