Murlan Kaufman: Difference between revisions
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Murlan Kaufman was born in Portland OR on July 14, 1937. | [[File:Murlan Kaufman.jpg|thumb|200px|right]] | ||
'''Murlan Kaufman''' was born in Portland, OR on July 14, 1937. | |||
He earned a BSEE in 1959 and MSEE in 1968 at Oregon State University. | He earned a BSEE in 1959 and MSEE in 1968 at Oregon State University. | ||
= Career = | == Career == | ||
Four summers working for Tek while attending Oregon State University | *Four summers working for Tek while attending Oregon State University | ||
June 1959 to January 1961 at General Electric in New York and Wisconsin | *June 1959 to January 1961 at General Electric in New York and Wisconsin | ||
January 1961 Design Engineer at Tek until retirement in August 1999 | *January 1961 Design Engineer at Tek until retirement in August 1999 | ||
= Tek Products = | == Tek Products == | ||
* Designed [[P6032]], [[CT-1]], [[CT-2]] and [[114]] pulse generator | * Designed [[P6032]], [[CT-1]], [[CT-2]] and [[114]] pulse generator | ||
* Inherited and completed design for [[R293]] pulse generator and [[184]] time mark generator | * Inherited and completed design for [[R293]] pulse generator and [[184]] time mark generator | ||
* Designed [[S-51]] 18 GHz Countdown and [[3T5]] auto triggering circuit | * Designed [[S-51]] 18 GHz Countdown and [[3T5]] auto triggering circuit | ||
* [[7B50]], [[7B51]], [[7B70]] and [[7B71]] | * [[7B50]], [[7B51]], [[7B70]] and [[7B71]] − inherited and completed design | ||
* [[485]] | * [[485]] − project Leader of the horizontal section | ||
* [[7844]] | * [[7844]] − inherited and completed as project manager | ||
* [[7D01]] [[DF1]] and [[DF2]] | * [[7D01]], [[DF1]] and [[DF2]] − project manager | ||
* [[DAS9129]] | * [[DAS9129]] − project manager for development of the color display logic analyzer | ||
* 11400 Series ([[11401]], [[11402]], [[11403]]) | * 11400 Series ([[11401]], [[11402]], [[11403]]) − assistant project manager and responsible for the touch panel and display | ||
* [[11802]] | * [[11802]] − project manager for sampling mainframe and [[SD-51]] 21 GHz trigger head | ||
* [[11A81]], [[11A34V]] and [[11T5H]] | * [[11A81]], [[11A34V]] and [[11T5H]] − managed development | ||
* [[THS700]] series | * [[THS700]] series − high voltage isolated front end design | ||
* Bipolar and BiCMOS IC design for TDS200, TDS300, TDS700 and TDS3000 series oscilloscopes | * Bipolar and BiCMOS IC design for TDS200, TDS300, TDS700 and TDS3000 series oscilloscopes | ||
= Patents = | == Patents == | ||
* [[Media:US3530315.pdf|Jitter Free Triggering Circuit 3,530,315]], filed March 1968 | * [[Media:US3530315.pdf|Jitter Free Triggering Circuit 3,530,315]], filed March 1968 | ||
* [[Media:US4488093.pdf|Color Shadow Mask CRT 4,488,093 with Doug Haines and Keith Taylor]], filed Oct 1982 | * [[Media:US4488093.pdf|Color Shadow Mask CRT 4,488,093 with Doug Haines and Keith Taylor]], filed Oct 1982 | ||
* [[Media:US6275257.pdf|Hold off By TV Fields 6,275,257 with Jim Tallman]], filed Oct 1998 | * [[Media:US6275257.pdf|Hold off By TV Fields 6,275,257 with Jim Tallman]], filed Oct 1998 | ||
= Publications = | == Publications == | ||
* Current Measurements at Nanosecond Speeds, Engineering Design News, October 1965 | * Current Measurements at Nanosecond Speeds, Engineering Design News, October 1965 | ||
* How Fast Does Your CRT Write? Electronic Design, July 1975 | * How Fast Does Your CRT Write? Electronic Design, July 1975 | ||
| Line 33: | Line 34: | ||
* Expression of the Properties of Logic Analyzers, International Electrotechnical Commission, IEC Standard, Publication 776, 1983 | * Expression of the Properties of Logic Analyzers, International Electrotechnical Commission, IEC Standard, Publication 776, 1983 | ||
= Other = | == Other == | ||
* Coordinated HW program development for 8002 with Millennium Information Systems in CA for 6 months in 1977 | * Coordinated HW program development for 8002 with Millennium Information Systems in CA for 6 months in 1977 | ||
* Secretariat on International Electrotechnical Commission WG4 to develop a Logic analyzer standard with inputs from HP, Biomation, Marconi, Schlumberger, meetings in Oslo, London and Budapest, 1977-84 | * Secretariat on International Electrotechnical Commission WG4 to develop a Logic analyzer standard with inputs from HP, Biomation, Marconi, Schlumberger, meetings in Oslo, London and Budapest, 1977-84 | ||
* Member of corporate technology team for color shutter and A to D conversion, 1981-82 | * Member of corporate technology team for color shutter and A to D conversion, 1981-82 | ||
* Member of Electronic Technical Advisory Committee (EITAC) for the US Dept. of Commerce for export regulations; active in rebuilding controls, meeting 4 times/year in WDC, 1989-96 | * Member of Electronic Technical Advisory Committee (EITAC) for the US Dept. of Commerce for export regulations; active in rebuilding controls, meeting 4 times/year in WDC, 1989-96 | ||
* With Marketing, introduced products in the US, Europe and Japan | * With Marketing, introduced products in the US, Europe and Japan | ||
<gallery> | <gallery> | ||
| Line 44: | Line 45: | ||
Murlan 1982.jpeg | Murlan 1982.jpeg | ||
</gallery> | </gallery> | ||
[[Category:Tektronix people]] | |||
Revision as of 03:21, 3 February 2021
Murlan Kaufman was born in Portland, OR on July 14, 1937. He earned a BSEE in 1959 and MSEE in 1968 at Oregon State University.
Career
- Four summers working for Tek while attending Oregon State University
- June 1959 to January 1961 at General Electric in New York and Wisconsin
- January 1961 Design Engineer at Tek until retirement in August 1999
Tek Products
- Designed P6032, CT-1, CT-2 and 114 pulse generator
- Inherited and completed design for R293 pulse generator and 184 time mark generator
- Designed S-51 18 GHz Countdown and 3T5 auto triggering circuit
- 7B50, 7B51, 7B70 and 7B71 − inherited and completed design
- 485 − project Leader of the horizontal section
- 7844 − inherited and completed as project manager
- 7D01, DF1 and DF2 − project manager
- DAS9129 − project manager for development of the color display logic analyzer
- 11400 Series (11401, 11402, 11403) − assistant project manager and responsible for the touch panel and display
- 11802 − project manager for sampling mainframe and SD-51 21 GHz trigger head
- 11A81, 11A34V and 11T5H − managed development
- THS700 series − high voltage isolated front end design
- Bipolar and BiCMOS IC design for TDS200, TDS300, TDS700 and TDS3000 series oscilloscopes
Patents
- Jitter Free Triggering Circuit 3,530,315, filed March 1968
- Color Shadow Mask CRT 4,488,093 with Doug Haines and Keith Taylor, filed Oct 1982
- Hold off By TV Fields 6,275,257 with Jim Tallman, filed Oct 1998
Publications
- Current Measurements at Nanosecond Speeds, Engineering Design News, October 1965
- How Fast Does Your CRT Write? Electronic Design, July 1975
- Pick a Logic Analyzer That is Right for Your Job, Instrument and Control Systems, February 1977
- Expression of the Properties of Logic Analyzers, International Electrotechnical Commission, IEC Standard, Publication 776, 1983
Other
- Coordinated HW program development for 8002 with Millennium Information Systems in CA for 6 months in 1977
- Secretariat on International Electrotechnical Commission WG4 to develop a Logic analyzer standard with inputs from HP, Biomation, Marconi, Schlumberger, meetings in Oslo, London and Budapest, 1977-84
- Member of corporate technology team for color shutter and A to D conversion, 1981-82
- Member of Electronic Technical Advisory Committee (EITAC) for the US Dept. of Commerce for export regulations; active in rebuilding controls, meeting 4 times/year in WDC, 1989-96
- With Marketing, introduced products in the US, Europe and Japan
