1 row is stored for this page
| Field | Field type | Value |
|---|
| _creationDate | Datetime | 2021-08-31 11:29:48 AM |
| _modificationDate | Datetime | 2021-08-31 11:29:48 AM |
| _categories | List of String, delimiter: | | Patents |
| _isRedirect | Boolean | No |
| _pageID | Integer | 28,618 |
| _pageName | Page | Patent US 5072369A |
| _pageTitle | String | Patent US 5072369A
|
| _pageNamespace | Integer | 0 |
1 row is stored for this page
| Field | Field type | Value |
|---|
| Office | String | US |
| Number | String | 5072369A |
| Title | String | Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates |
| Inventors | List of Page, delimiter: ; | John G. Theus • Jeffrey L. Beachy |
| Company | List of Page, delimiter: ; | Tektronix Inc |
| Filing_date | Date | 1989-04-07 |
| Grant_date | Date | 1991-12-10 |
| Cites | List of Page, delimiter: ; | |
| Links | List of Page, delimiter: ; | |