DC501: Difference between revisions

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(Added service note 050-1276-00)
(Fixed rear interface pinout table)
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==Rear Interface ==
==Rear Interface ==
<div style="column-count:3;-moz-column-count:3;-webkit-column-count:3">
{| class="wikitable"
* 28B Second decimal point (D2) output
|-
* 27A Internal scan clock disable input
! Connector Pin
* 27B MHz light output
! Signal
* 26A Reset input/output
|-
* 25A TS0 (Time Slot Zero) output
| 28B || Second decimal point (D2) output
* 25B External scan clock input
|-
* 24B Internal scan clock (2 kHz) output
| 27A || Internal scan clock disable input
* 23B Overflow output
|-
* 22B MSD (most significant digit)
| 27B || MHz light output
* 20B 2<sup>8</sup> BCD output, serial by digit
|-
* 20A 2<sup>4</sup> BCD output, serial by digit
| 26A || Reset input/output
* 21B 2<sup>2</sup> BCD output, serial by digit
|-
* 19A 2<sup>1</sup> BCD output, serial by digit
| 25A || TS0 (Time Slot Zero) output
* 19B Data Good output
|-
* 17A Signal input ground
| 25B || External scan clock input
* 16A Signal input
|-
</div>
| 24B || Internal scan clock (2 kHz) output
|-
| 23B || Overflow output
|-
| 22B || MSD (most significant digit)
|-
| 20B || 2<sup>8</sup> BCD output, serial by digit
|-
| 20A || 2<sup>4</sup> BCD output, serial by digit
|-
| 21B || 2<sup>2</sup> BCD output, serial by digit
|-
| 19A || 2<sup>1</sup> BCD output, serial by digit
|-
| 19B || Data Good output
|-
| 17A || Signal input ground
|-
| 16A || Signal input
|}


==Pictures==
==Pictures==

Revision as of 05:44, 11 September 2022

Tektronix DC501
basic 100 MHz frequency counter
Tektronix DC501

Produced from 1972 to 1980

Manuals
Manuals – Specifications – Links – Pictures

The Tektronix DC501 is a basic 100 MHz frequency counter plug-in for the TM500 system.


Key Specifications

Input frequency 10 Hz to 100 MHz
Gate time 10 ms to 10 s in decade steps, plus Manual (totalize count of up to 107 events)
Resolution 7 digits
Display 7-digit LED, overflow indicator
Input impedance 1 MΩ // 20 pF, ×5/×10/×50 attenuator (front) or 50 Ω // 20 pF (rear)
Time base stability ≤1×10-5; Opt. 1, ≤5×10-7 (0°C to +50°C after ½h warm-up)
Time base drift ≤1×10-5; Opt. 1, ≤1×10-7 (per month)

Options

  • Option 1 – 5 MHz TCXO with 1:5 divider
  • Option 2 – Automatic Gate Control and Readout Scaling Circuit (automatically selects the 0 .1-, 1-, or 10-second measurement interval to display the largest number of digits without overflow)

Rear Interface

Connector Pin Signal
28B Second decimal point (D2) output
27A Internal scan clock disable input
27B MHz light output
26A Reset input/output
25A TS0 (Time Slot Zero) output
25B External scan clock input
24B Internal scan clock (2 kHz) output
23B Overflow output
22B MSD (most significant digit)
20B 28 BCD output, serial by digit
20A 24 BCD output, serial by digit
21B 22 BCD output, serial by digit
19A 21 BCD output, serial by digit
19B Data Good output
17A Signal input ground
16A Signal input

Pictures