DF1

The Tektronix DF1 is a display formatter for use with the 7D01 logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared.

The DF1 is built around a Motorola 6800 microprocessor with two 2K×8 masked ROMs and sixteen 1K×1 SRAMs (2101). It attaches to the 7D01 through a 50-pin D-sub connector on the right side panel.

Project manager for the DF1 was Murlan Kaufman.

Key Specifications

External Read Clock	Frequency Range 100 kHz to 500 kHz Duty Cycle 50% within 5%.
Display	Vertical Size — Adjustable from 6.9 div or less to at least 8.1 div from the top of the first line of DF1 readout to the bottom of the last line of DF1 readout. Vertical Position — Adjustable to vertical center of display area in any calibrated 7000-series mainframe. Horizontal Position — Adjustable to horizontal center of display area in any calibrated 7000-series mainframe.
Output Signals	Reset Logic Voltage Level — LO: +0.4 V or less at 2 mA. HI: at least +2.4 V at 2 mA. Waveshape — Positive-going rectangular pulse. Duration — 100 μs within 50 μs when used with the 7D01 internal read clock.

Pictures

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  Front

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  Internal

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  Side connector

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  7D01 and DF1 in 7313