6R1: Difference between revisions

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6R1 (view source)

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(bistable multivibrators) are implemented in the 6R1 using the classic cross-coupled  
(bistable multivibrators) are implemented in the 6R1 using the classic cross-coupled  
transistor pair.  The counter is composed of several of these flip-flop subcircuits,
transistor pair.  The counter is composed of several of these flip-flop subcircuits,
as are various other state machines in the 6R1.
as are various other state machines in the 6R1. All of the active circuitry of the
6R1 is on small plug-in printed circuit boards.  There are twelve different boards
labeled A through L.  The 6R1 contains more than one of some of the boards, seventeen
boards in total.
 
*Card A: COUNTER (6R1 has four of these)
*Card B: DIVIDE BY 1,2,5
*Card C: MASTER GATE
*Card D: SIGNAL COMPARATOR (6R1 has two of these)
*Card E: VOLTMETER
*Card F: UPPER LIMIT NO-GO
*Card G: LOWER LIMIT NO-GO
*Card H: LIGHT LIMIT DRIVER
*Card I: DIVIDE BY 10
*Card J: ANALOG DISPLAY
*Card K: 0% ZONE
*Card L: MEMORY (6R1 has two of these)


When a 6R1 is used in a 567 with a [[3T77]], the horizontal sweep signal is
When a 6R1 is used in a 567 with a [[3T77]], the horizontal sweep signal is
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to pin 7 of the 0% zone card.   
to pin 7 of the 0% zone card.   


== 0% ZONE Card ==
== Card K: 0% ZONE ==
The primary purpose if the 0% ZONE circuit is to produce
The primary purpose if the 0% ZONE circuit is to produce
a signal that instructs the memory circuits to sample and hold the voltages at their
a signal that instructs the memory circuits to sample and hold the voltages at their
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is the logical complement of the +0% signal, generated by common-emitter inverter Q64.
is the logical complement of the +0% signal, generated by common-emitter inverter Q64.


== MEMORY Card ==
== Card L: MEMORY ==
The 6R1 contains two MEMORY cards, one for vertical input A and one for vertical input B.
The 6R1 contains two MEMORY cards, one for vertical input A and one for vertical input B.
Each MEMORY card contains two sample and hold circuits.
Each MEMORY card contains two sample and hold circuits.
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is trapped on the the capacitor until the next sampling pulse.  (V_cap = Q_cap / C).
is trapped on the the capacitor until the next sampling pulse.  (V_cap = Q_cap / C).


The 100% zone sample and hold circuit gets its sampling signals from the 100% zone detector circuit which
The 100% zone sample and hold circuit gets its sampling signals  
is also on the MEMORY card.  The purpose of the 100% zone detector circuit is to generate a logic signal
from the 100% zone detector circuit which
that is true when the sweep is within the 100% zone.  The horizontal position of the 100% zone is variable  
is also on the MEMORY card.  The purpose of the 100% zone detector  
using the "A 100% ZONE SET" and "B 100% ZONE SET" controls on the front of the 6R1.  One pin 12, the MEMORY
circuit is to generate a logic signal
card get the +GATE signal, which is high while the timing unit (3T77, for example) is sweeping.  Between sweeps,
that is true when the sweep is within the 100% zone.   
the +GATE signal is low, 0V, which turns off Q3.  With Q3 off, Q13 and Q23 have no collector current, so D13 and
The horizontal position of the 100% zone is variable  
D23 have no current.  When the sweep starts, the +GATE signal goes to +20V, and the emitter voltage of Q3 follows.
using the "A 100% ZONE SET" and "B 100% ZONE SET" controls  
Tunnel diodes D13 and D23 operate in a bistable mode.  When the sweep ramp starts, both diodes are in their low-voltage
on the front of the 6R1.  One pin 12, the MEMORY
state.  When the sweep enters the left edge of the 100% zone, D23 switches to the high-voltage state, while D13 remains
card get the +GATE signal, which is high while the  
in the low-voltage state.  This causes the base voltage of Q33 to rise, turning Q33 off, and it causes the base voltage
timing unit (3T77, for example) is sweeping.  Between sweeps,
of Q43 to fall, turning Q43 off.  This turns on the sampling gate, as discussed above for the 0% sample and hold circuit.
the +GATE signal is low, 0V, which turns off Q3.   
When the sweep ramp reaches a voltages the corresponds to the right edge of the 100% zone, D13 switches to the high-voltage
With Q3 off, Q13 and Q23 have no collector current,  
state, turning on Q14, which turns off the sampling gate.  The sampling gate connects the vertical input signal to the  
so D13 and D23 have no current.   
holding capacitor when D23 is in the high-voltage state and D13 is in the low-voltage state.  At the end of the sweep,
When the sweep starts, the +GATE signal goes to +20V,  
the +GATE signal goes down to 0V.  That turns off Q3 and returns D13 and D23 to the original low-voltage state.
and the emitter voltage of Q3 follows.
Tunnel diodes D13 and D23 operate in a bistable mode.   
When the sweep ramp starts, both diodes are in their low-voltage state.   
When the sweep enters the left edge of the 100% zone, D23 switches  
to the high-voltage state, while D13 remains in the low-voltage state.   
This causes the base voltage of Q33 to rise, turning Q33 off,  
and it causes the base voltage of Q43 to fall, turning Q43 off.   
This turns on the sampling gate, as discussed above for the  
0% sample and hold circuit.
When the sweep ramp reaches a voltages the corresponds to  
the right edge of the 100% zone, D13 switches to the high-voltage
state, turning on Q14, which turns off the sampling gate.   
The sampling gate connects the vertical input signal to the  
holding capacitor when D23 is in the high-voltage state and  
D13 is in the low-voltage state.  At the end of the sweep,
the +GATE signal goes down to 0V.  That turns off Q3 and  
returns D13 and D23 to the original low-voltage state.


[http://w140.com/tek_6r1_schem.pdf 6R1 Schematics]
[http://w140.com/tek_6r1_schem.pdf 6R1 Schematics]
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