318: Difference between revisions

55 bytes added ,  21 January 2022
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{{BeginSpecs}}
{{BeginSpecs}}
{{Spec | Probes | [[P6451]] (8-channel) and [[P6107]] (trigger/serial) }}
{{Spec | Probes | [[P6451]] (8-channel) and [[P6107]] (trigger/serial) }}
{{Spec | Number of channels | 16 channels }}
{{Spec | Channels | 16 channels }}
{{Spec|Glitch Detection|On Pod A and B (16 Channels)}}
{{Spec | Glitch detection | On Pod A and B (16 Channels)}}
{{Spec|Minimum Logic Swing|500mV pp}}
{{Spec | Minimum logic swing |500 mV<sub>p-p</sub>}}
{{Spec|Maximum Logic Swing|-15V to +10V}}
{{Spec | Maximum logic swing |–15 V to +10 V}}
{{Spec|Maximum non-destructive|±40V}}
{{Spec | Maximum input |±40 V non-destructive}}
{{Spec|Glitch Data Width|5ns min}}
{{Spec | Glitch data width| 5 ns min}}
{{Spec|Clock Source|Internal or external}}
{{Spec | Clock source | Internal or external}}
{{Spec|Data Setup Time | 13ns min, 8ns typ.}}
{{Spec | Data setup time | 13 ns min, 8 ns typ.}}
{{Spec|Data Hold Time | 0ns}}
{{Spec | Data hold time | 0 ns}}
{{Spec|Minimum Clock Period|20ns}}
{{Spec | Minimum clock period | 20 ns}}
{{Spec|Memory Depth|  
{{Spec | Memory |
* Reference Memory:  16 x 256 bits
* Reference Memory:  16 x 256 bits
* Aquisition Memory: 16 x 256 bits
* Aquisition Memory: 16 x 256 bits
* Glitch Memory: 16 x 256 bits
* Glitch Memory:     16 x 256 bits
}}
}}
{{Spec | Features |  
{{Spec | Features |