P6442: Difference between revisions
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{{Probe Sidebar | |||
|manufacturer=Tektronix | |||
|model=P6442 | |||
|summary=16-channel logic analyzer probe | |||
|image=P6442.JPG | |||
|caption=Tektronix P6442 | |||
|for=1220 1225 1230 | |||
|introduced=(?) | |||
|discontinued=(?) | |||
|manuals= | |||
* ''please add'' [[Category:Manual needed]] | |||
}} | |||
The '''Tektronix P6442''' channel state/timing probe can be used with the [[1230]], [[1225]] and [[1220]] logic analyzers. | The '''Tektronix P6442''' channel state/timing probe can be used with the [[1230]], [[1225]] and [[1220]] logic analyzers. | ||
It is a 16-channel data acquisition probe TTL threshold probe. The '''P6442''' has three external lines and one qualifier line. | It is a 16-channel data acquisition probe TTL threshold probe. The '''P6442''' has three external lines and one qualifier line. It uses the [[174-0752-00]], [[174-0763-00]], and [[174-0764-00]] lead set. | ||
'''Note from operators manual:''' | |||
<blockquote> | |||
''You cannot mix P6442 probes with [[P6443]] or [[P6444]] probes to take an acquisition.<br />If you acquire data on P6442 probes at the same time you try to sample data on P6443/P6444 probes, the acquired data from the P6443/P6444 probes will be invalid.'' | |||
</blockquote> | |||
{ | ==Specifications== | ||
The probe is composed solely of TTL level integrated circuits. The construction of the probe is made of two board stacked on top of each other. | |||
The pin-out of the probe is given. (looking from the front) | |||
{| class="wikitable" | |||
! colspan="2" style="font-style:italic;" | Notch | |||
! colspan="3" | | |||
! rowspan="3" | | |||
! colspan="2" style="font-style:italic;" | Notch | |||
! colspan="3" | | |||
! rowspan="3" | | |||
! colspan="2" style="font-style:italic;" | Notch | |||
! colspan="3" | | |||
|- | |||
| EXT | |||
| EXT | |||
| EXT | |||
| CLK | |||
| CLK | |||
| CLK | |||
| D14 | |||
| D12 | |||
| D10 | |||
| D8 | |||
| CLK | |||
| D6 | |||
| D4 | |||
| D2 | |||
| D0 | |||
|- | |||
| EXT | |||
| EXT | |||
| EXT | |||
| QUAL | |||
| QUAL | |||
| GND | |||
| D15 | |||
| D13 | |||
| D11 | |||
| D9 | |||
| GND | |||
| D7 | |||
| D5 | |||
| D3 | |||
| D1 | |||
|} | |||
==Pictures== | |||
<gallery> | <gallery> | ||
Tek p6442 1.jpg | |||
Tek p6442 2.jpg | |||
P6442inside.JPG | P6442inside.JPG | ||
P6442bottomboard.JPG | |||
</gallery> | </gallery> | ||
[[Category:Logic analyzer probes]] | [[Category:Logic analyzer probes]] | ||
Latest revision as of 04:14, 13 August 2023
The Tektronix P6442 channel state/timing probe can be used with the 1230, 1225 and 1220 logic analyzers.
It is a 16-channel data acquisition probe TTL threshold probe. The P6442 has three external lines and one qualifier line. It uses the 174-0752-00, 174-0763-00, and 174-0764-00 lead set.
Note from operators manual:
You cannot mix P6442 probes with P6443 or P6444 probes to take an acquisition.
If you acquire data on P6442 probes at the same time you try to sample data on P6443/P6444 probes, the acquired data from the P6443/P6444 probes will be invalid.
Specifications
The probe is composed solely of TTL level integrated circuits. The construction of the probe is made of two board stacked on top of each other.
The pin-out of the probe is given. (looking from the front)
| Notch | Notch | Notch | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EXT | EXT | EXT | CLK | CLK | CLK | D14 | D12 | D10 | D8 | CLK | D6 | D4 | D2 | D0 | ||
| EXT | EXT | EXT | QUAL | QUAL | GND | D15 | D13 | D11 | D9 | GND | D7 | D5 | D3 | D1 | ||
