P7001: Difference between revisions
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(Added short description of sample&Hold card) |
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{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Bandwith | | {{Spec | Bandwith | 175 MHz }} | ||
{{Spec | Resolution | 10 bit (V), 9 bit (H) }} | {{Spec | Resolution | 10 bit (V), 9 bit (H) }} | ||
{{Spec | Memory | four waveforms, 512 samples each (4K × 10 bit core, or multiple 1k × 10 bit or 2k × 10 bit RAM boards) }} | {{Spec | Memory | four waveforms, 512 samples each (4K × 10 bit core, or multiple 1k × 10 bit or 2k × 10 bit RAM boards) }} | ||
{{Spec | Sampling rate | | {{Spec | Sampling rate | 150 kHz ±30 kHz }} | ||
{{Spec | Single shot performance | | {{Spec | Single shot performance | 500 μs/Div }} | ||
{{Spec | External interface | 16 bit parallel, proprietary "[[CP bus]]" (dual 37-pin [[Sub-D connector]]s) interfacing with Tektronix CP-1100 or CP-4100 series controllers }} | {{Spec | External interface | 16 bit parallel, proprietary "[[CP bus]]" (dual 37-pin [[Sub-D connector]]s) interfacing with Tektronix CP-1100 or CP-4100 series controllers }} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
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To provide maximum flexibility all P7001 circuit cards are connected over an 16 bit asynchronous bus with 13 address lines. The bus is mostly implemented as etched lines on the Main Interface Board. Only some High speed signals are sent through coaxial cables that connect to the cards using [[Peltola connector]]s. A serially connected line, or daisy chain, in the bus establishes device priority. This signal is called "Data Channel Grant Line". Each card has a specific location in the DPO. The position determines the priority that each card has in the use of the address and data buses. Unused slots must be fitted with a jumper card to close the daisy chain. | To provide maximum flexibility all P7001 circuit cards are connected over an 16 bit asynchronous bus with 13 address lines. The bus is mostly implemented as etched lines on the Main Interface Board. Only some High speed signals are sent through coaxial cables that connect to the cards using [[Peltola connector]]s. A serially connected line, or daisy chain, in the bus establishes device priority. This signal is called "Data Channel Grant Line". Each card has a specific location in the DPO. The position determines the priority that each card has in the use of the address and data buses. Unused slots must be fitted with a jumper card to close the daisy chain. | ||
===Memory=== | ===Memory=== | ||
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'''Design Team''' | '''Design Team''' | ||
<br />Notable Members of the Design Team were | <br />Notable Members of the Design Team were [[Hiro Moriyasu]], [[Bruce Hamilton]], [[Luis Navarro]], [[Bob Shand]] and [[Jack Gilmore]]. | ||
<gallery> | <gallery> | ||
Tek_P7001_Designteam.jpg|Key design Team of the P7001 | Tek_P7001_Designteam.jpg|Key design Team of the P7001 | ||
</gallery> | </gallery> | ||