7D01: Difference between revisions

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{{Plugin Sidebar |

{{Plugin Sidebar

manufacturer=Tektronix | type=7D01 |

|manufacturer=Tektronix

summary=Logic Analyzer |

|series=7000-series scopes

image=Tek 7D01 Front 2.jpg |

|type=7D01

caption=Tektronix 7D01 without display formatter |

|summary=Logic Analyzer

introduced=1976 |

|image=Tek 7D01 Front 2.jpg

discontinued=1985 |

|caption=Tektronix 7D01 without display formatter

~~series=7000-series scopes~~|

|introduced=1976

manuals=

|discontinued=1985

|manuals=

* [[Media:070-2205-02.pdf|7D01 Operators Manual (OCR, PDF)]]

* [[Media:070-2206-00.pdf|7D01 Instruction Manual, part no 070-2206-00 (OCR, PDF)]]

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The '''Tektronix 7D01''' is a 16-channel logic analyzer plug-in for the [[7000-series scopes]] that takes two [[P6451]] 8+1 channel probes.

~~The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs.~~ When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).

When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).

When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available.

The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier .

The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to 1.4 V and the second probe (9-15, QUAL) to the variable voltage.

The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.

A built-in word recognizer can trigger on any combination of the 16 data signals plus an external qualifier ~~input~~. The ~~recorgnizer~~'s output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.

A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs.

The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.

The 7D01 ~~has an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable. It~~ is also compatible with the [[DL2]] or [[DL502]] latch (glitch detector) that plugs in between the P6451 probes and the 7D01's inputs.

The 7D01 is also compatible with the [[DL2]] or [[DL502]] latch (glitch detector) that plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.

Project manager for the 7D01 was [[Murlan Kaufman]].

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* 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)

}}

{{Spec | Sampling Rate | 10 ns to 5 ms per sample (~~1—2—5~~) or external clock up to 50 MHz}}

{{Spec | Sampling Rate | 10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz}}

{{Spec | Trigger Sources |

* external

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==Internals==

The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits. The ~~−5 V~~ ECL ~~supply is~~ generated by a 555-driven switcher powered off the ±15 V rails.

The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs.

The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.

The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails.

There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable. ''(Any known uses?)''

==Notes==

@@ Line 1: / Line 1: @@
-{{Plugin Sidebar  |
+{{Plugin Sidebar
-manufacturer=Tektronix | type=7D01 |
+|manufacturer=Tektronix
-summary=Logic Analyzer |
+|series=7000-series scopes
-image=Tek 7D01 Front 2.jpg |
+|type=7D01
-caption=Tektronix 7D01 without display formatter |
+|summary=Logic Analyzer
-introduced=1976 |
+|image=Tek 7D01 Front 2.jpg
-discontinued=1985 |
+|caption=Tektronix 7D01 without display formatter
-series=7000-series scopes|
+|introduced=1976
-manuals=
+|discontinued=1985
+|manuals=
 * [[Media:070-2205-02.pdf|7D01 Operators Manual (OCR, PDF)]]
 * [[Media:070-2206-00.pdf|7D01 Instruction Manual, part no 070-2206-00 (OCR, PDF)]]
@@ Line 17: / Line 18: @@
 The '''Tektronix 7D01''' is a 16-channel logic analyzer plug-in for the [[7000-series scopes]] that takes two [[P6451]] 8+1 channel probes.
-The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs.  When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
+When used by itself, it only displays a timing diagram that can be positioned and zoomed using analog controls, and uses the mainframe's [[7000 series readout system|readout system]] to indicate the cursor position (on top) and the binary data pattern at the cursor location (using the two bottom readout fields).
 When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available.
+The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier .
+The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to 1.4 V and the second probe (9-15, QUAL) to the variable voltage.
 The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
-A built-in word recognizer can trigger on any combination of the 16 data signals plus an external qualifier input.  The recorgnizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
+A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs.
+The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
-The 7D01 has an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable.  It is also compatible with the  [[DL2]] or [[DL502]] latch (glitch detector) that plugs in between the P6451 probes and the 7D01's inputs.
+The 7D01 is also compatible with the [[DL2]] or [[DL502]] latch (glitch detector) that plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.
 Project manager for the 7D01 was [[Murlan Kaufman]].
@@ Line 34: / Line 39: @@
 * 16 channels at 254 bits/channel, maximum external clock period 40 ns (25 MHz)
 }}
-{{Spec | Sampling Rate | 10 ns to 5 ms per sample (1—2—5) or external clock up to 50 MHz}}
+{{Spec | Sampling Rate | 10 ns to 5 ms per sample (1–2–5) or external clock up to 50 MHz}}
 {{Spec | Trigger Sources |
 * external
@@ Line 44: / Line 49: @@
 ==Internals==
-The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits. The −5 V ECL supply is generated by a 555-driven switcher powered off the ±15 V rails.
+The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf ECL and TTL logic ICs.
+The data path, acquisition memory, and clock generator in the 7D01 are built using ECL circuits.
+The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails.
+There is an internal DB-25 data output connector and a front-panel cut-out for the corresponding cable.  ''(Any known uses?)''
 ==Notes==

7D01: Difference between revisions

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