067-0587-02: Difference between revisions

067-0587-02 (view source)

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 The clock is delayed, amplified and limited, then fed to a Schottky-diode based pulse shaper with L-C compensating networks. The output pulse has a rise time of max. 150 picoseconds with less than 2% aberrations.
-The staircase generator for Gain mode is implemented using a 4 bit count and multiplexer.  The 0-volt step (No. 6) is held for five counts, producing a brighter trace to allow easy alignment with the center of the screen.
+The staircase generator for Gain mode is implemented using a 4 bit counter and multiplexer.  The 0-volt step (No. 6) is held for five counts, producing a brighter trace to allow easy alignment with the center of the screen.
-For bandwidth measurements, there is a leveler circuit with a [[155-0183-00|differential diode detector]] controlling an amplifier's gain in an AGC loop.
+For bandwidth measurements, there is a leveler circuit with a [[155-0183-00|differential diode detector]] controlling an amplifier's gain in an AGC loop.  '''NB:''' The response is not specified below 3 MHz.
 The 067-0587-02 is based on a number of Tektronix custom ICs from the 1 GHz [[7104]] scope generation, such as the [[155-0160-00|155-0160-00 trigger amplifier + source select chip]] and the [[155-0175-00|155-0175-00 trigger amplifier chip]].