DL2: Difference between revisions
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{{Spec |Minimum clock period | 20 ns }} | {{Spec |Minimum clock period | 20 ns }} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
==Internals== | |||
The data path in the DL2 is built using standard 100k ECL circuits. The –4.8 V and –2 V ECL supplies are generated by a 555-driven switcher powered off the ±15 V rails (same board as in the [[7D01]]). | |||
==Links== | ==Links== | ||