7D02: Difference between revisions
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{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Channels | up to 52 - 28 (optionally 44) synchronous, 8 sync or async (timing option) }} | {{Spec | Channels | up to 52 - 28 (optionally 44) synchronous, 8 sync or async (timing option) }} | ||
{{Spec | Inputs | (standard 7D02) 8 | {{Spec | Inputs | (standard 7D02) 8 data, 16 address, 10 control, 1 ext. trigger }} | ||
{{Spec | Memory | 256 words }} | {{Spec | Memory | 256 words }} | ||
{{Spec | Sampling Rate | up to 10 MHz }} | {{Spec | Sampling Rate | up to 10 MHz }} | ||
{{Spec | Options | | {{Spec | Options | | ||
* Option 01 − Timing | * Option 01 − Timing: Adds 8 additional asynchronous channels with sampling rates from 5 ms to 20 ns (up to 50 MHz) using a [[P6451]] logic probe;<br />255-word acquisition memory, 255-word glitch memory, 9-bit word recognizer | ||
* Option 03 − Expansion: Adds 8 | * Option 03 − Expansion: Adds 8 data and 8 address lines to 7D02, required for 16 bit microprocessors. | ||
}} | }} | ||
{{EndSpecs}} | {{EndSpecs}} |