DC501: Difference between revisions

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==Specifications==
{{BeginSpecs}}
[[Category:Specifications needed]] ''please add''
{{Spec | Input frequency | 10 Hz to 100 MHz  }}
{{Spec | Gate time | 10 ms to 10 s in decade steps, plus Manual (totalize count of up to 10<sup>7</sup> events) }}
{{Spec | Resolution | 7 digits }}
{{Spec | Display | 7-digit LED, overflow indicator }}
{{Spec | Input impedance | 1 MΩ // 20 pF, ×5/×10/×50 attenuator (front) or 50 Ω // 20 pF (rear) }}
{{Spec | Time base stability | ≤1×10<sup>-5</sup>; Opt. 1, ≤5×10<sup>-7</sup> (0°C to +50°C after ½h warm-up) }}
{{Spec | Time base drift | ≤1×10<sup>-5</sup>; Opt. 1, ≤1×10<sup>-7</sup> (per month) }}
{{EndSpecs}}
 
==Options==
* Option 1 – 5 MHz TCXO with 1:5 divider
* Option 2 – Automatic Gate Control and Readout Scaling Circuit (automatically selects the 0 .1-, 1-, or 10-second measurement interval to display the largest number of digits without overflow)
==Rear Interface ==
 
<div style="column-count:3;-moz-column-count:3;-webkit-column-count:3">
* 28B Second decimal point (D2) output
* 27A Internal scan clock disable input
* 27B MHz light output
* 26A Reset input/output
* 25A TS0 (Time Slot Zero) output
* 25B External scan clock input
* 24B Internal scan clock (2 kHz) output
* 23B Overflow output
* 22B MSD (most significant digit)
* 20B 2<sup>8</sup> BCD output, serial by digit
* 20A 2<sup>4</sup> BCD output, serial by digit
* 21B 2<sup>2</sup> BCD output, serial by digit
* 19A 2<sup>1</sup> BCD output, serial by digit
* 19B Data Good output
* 17A Signal input ground
* 16A Signal input
</div>


==Pictures==
==Pictures==

Revision as of 03:43, 10 December 2019

Tektronix DC501
100 MHz frequency counter
Tektronix DC501

Produced from 1972 to 1980

Manuals
(All manuals in PDF format unless noted otherwise)
Manuals – Specifications – Links – Pictures

The Tektronix DC501 is a 100 MHz frequency counter plug-in for the TM500 system.


Key Specifications

Input frequency 10 Hz to 100 MHz
Gate time 10 ms to 10 s in decade steps, plus Manual (totalize count of up to 107 events)
Resolution 7 digits
Display 7-digit LED, overflow indicator
Input impedance 1 MΩ // 20 pF, ×5/×10/×50 attenuator (front) or 50 Ω // 20 pF (rear)
Time base stability ≤1×10-5; Opt. 1, ≤5×10-7 (0°C to +50°C after ½h warm-up)
Time base drift ≤1×10-5; Opt. 1, ≤1×10-7 (per month)

Options

  • Option 1 – 5 MHz TCXO with 1:5 divider
  • Option 2 – Automatic Gate Control and Readout Scaling Circuit (automatically selects the 0 .1-, 1-, or 10-second measurement interval to display the largest number of digits without overflow)

Rear Interface

  • 28B Second decimal point (D2) output
  • 27A Internal scan clock disable input
  • 27B MHz light output
  • 26A Reset input/output
  • 25A TS0 (Time Slot Zero) output
  • 25B External scan clock input
  • 24B Internal scan clock (2 kHz) output
  • 23B Overflow output
  • 22B MSD (most significant digit)
  • 20B 28 BCD output, serial by digit
  • 20A 24 BCD output, serial by digit
  • 21B 22 BCD output, serial by digit
  • 19A 21 BCD output, serial by digit
  • 19B Data Good output
  • 17A Signal input ground
  • 16A Signal input

Pictures