7D01: Difference between revisions
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* [[Media:070-2205-02.pdf|7D01 Operators Manual (OCR, PDF)]] | * [[Media:070-2205-02.pdf|7D01 Operators Manual (OCR, PDF)]] | ||
* [[Media:070-2206-00.pdf|7D01 Instruction Manual, part no 070-2206-00 (OCR, PDF)]] | * [[Media:070-2206-00.pdf|7D01 Instruction Manual, part no 070-2206-00 (OCR, PDF)]] | ||
* [http://w140.com/smb/7d01_sm.pdf 7D01 Instruction Manual, part no 070-2206-02 (OCR, PDF)] | * [http://w140.com/smb/7d01_sm.pdf 7D01 Instruction Manual, revised Oct 1982, part no 070-2206-02 (OCR, PDF)] | ||
* [http://w140.com/tekscope_1976vol8no2_7d01.pdf 7D01 Article in 1976 Volume 8 Number 2 Tekscope (PDF)] | * [http://w140.com/tekscope_1976vol8no2_7d01.pdf 7D01 Article in 1976 Volume 8 Number 2 Tekscope (PDF)] | ||
* [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976 (PDF)]] | * [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976 (PDF)]] |
Revision as of 02:31, 31 October 2020
Template:Plugin Sidebar 2 The Tektronix 7D01 is a logic analyzer plug-in for the 7000-series scopes. Compatible extension modules include the DF1 and DF2 display formatters and the DL2 or DL502 latch (glitch detector). The 7D01 takes two P6451 8+1 channel probes. The 7D01 does not contain a microprocessor and is built entirely from off-the-shelf logic ICs.
Key Specifications
Channels |
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Sampling Rate | 10 ns to 5 ms per sample (1—2—5) or external clock up to 50 MHz |
Trigger Sources |
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Notes
Note about external clock rates (from Jim Mauck):
When I was a Tek Service Technician I worked on the 7D01. For several years I tested every 7D01 I worked on (and that was a lot of them) with a 100 MHz external clock in 16 channel mode. I would use a DF2 and set it to reacquire continuously as long as the 7D01 memory was the same as the original data I stored into the DF2 memory. The analyzer would run for hours without error. The funny part is that it wasn't until I had been doing this for several years that I realized it wasn't specified to run at that frequency. I continued to test them that way even after I discovered my error. However the instrument exceeding the specifications might be due to the data source providing a generous setup and hold time relative to the active clock edge.