DF1

Manuals – Specifications – Links – Pictures

The Tektronix DF1, introduced in 1977, is a "display formatter" for use with the 7D01 logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared. The DF1 was introduced in 1977.

The Tektronix DF2, introduced in 1978, is the same as the DF1 with the exception of an added front-panel "Menu" key and an additional ROM (on a daughter board) that supports GPIB and ASCII modes.

The DF2 does not have a GPIB interface, it can only analyze external GPIB traffic. For this purpose, a 103-0209-00 GPIB to probe comb adapter was supplied with the DF2, which connects GPIB DIO1..DIO8 to CH8..CH15, DAV to the CLOCK input, ATN to CH7, EOI to CH6, SRQ to CH5, and REN to CH4. GPIB signals DAV, NRFD, NDAC and IFC brought out to pins on the connector. CH3..0 are user defined inputs that can track any of these signals, or others as needed. For GPIB analysis, bus data is acquired synchronously using the negative-going edge of the GPIB DAV (Data Valid) line as an external clock.

From TekScope V.8 N.4 1976:

Project manager for the DF1/DF2 was Murlan Kaufman, with Dave Lowry and Jeff Bradford doing the electrical and software design, and Ed Wolfe doing mechanical design. Roy Kaufman and Joe Gaudio, Evaluation Engineers, and Dave McCullough, Marketing Program Manager, also made valuable contributions. Special thanks are due to Jack Lyngdal and Nick Colvin, Manufacturing; Betty Spohn, ECB; Jan Bowden, Prototypes; and to everyone else who contributed to a a speedy, efficient completion of the project.

Key Specifications

Memory	One reference table memory, 1KB, same as 7D01 capacity (max. 16 channels at 254 bits/ch), plus 1KB display RAM
Display modes	7D01/DF1 or DF2 Timing: Standard 7D01 display – 4, 8 or 16 bits State table: Hexadecimal, octal, or binary formats; two tables (reference, 7D01 memory) of 17 lines of 16-bit words Map: Dot display of the 16 data channels in X-Y coordinate points. Each dot location represents one possible combination of up to 16 inputs to the 7D01. 7D01/DF2 GPIB: Displays 17 lines of decoded GPIB operations and/or ASCII data, and up to four user-defined input signal states. ASCII: Displays 17 lines of decoded ASCII character along with its binary, octal, or hex value, in either 8– or 16–bit modes.
Reset output	Positive 100 μs pulse, ≤0.4 V / ≥2.4 V

Links

Documents Referencing DF1

Document	Class	Title	Authors	Year	Links
Tekscope 1976 V8 N4 with Supplement.pdf	Article	A Display Formatter – The Indispensable Tool for the Data Domain	Dave Lowry • Jeff Bradford	1976	DF1 • 7D01
AX-3524.pdf	Application Note	Troubleshooting a Microprocessor (Logic Analyzer App Note #57K1.0)		1977	7D01 • DF1
Tek forum report 6.pdf	Article	A GPIB Analyzer	Bruce Ableidinger • Jeff Bradford	1979	7D01 • DF1 • DF2

Documents Referencing DF2

Document	Class	Title	Authors	Year	Links
Tekscope 1978 V10 N1.pdf	Article	New Products		1978	DF2 • P6303 • C-28 • 8001 • CT8100 • 4014-1
Tekscope 1978 V10 N2.pdf	Article	Unraveling the Mystery on the GPIB	Bruce Ableidinger	1978	DF2 • 7D01 • P6451 • GPIB
Tek forum report 11.pdf	Article	7D01-DF2 Delta-Time Readout	Bruce Ableidinger	1979	7D01 • DF2
Tek forum report 6.pdf	Article	A GPIB Analyzer	Bruce Ableidinger • Jeff Bradford	1979	7D01 • DF1 • DF2

Background

The DF2 started as a "G-Job". Tek Forum Report 6 (1979) says:

Bruce Ableidinger (Logic Development Products) and Jeff Bradford (also LDP) have developed a GPIB (General Purpose Interface Bus) analyzer that uses a 7D01 Logic Analyzer and a modified DF1 Display Formatter.

Interface-dependent and device-dependent messages handshaked across the GPIB can be displayed in a familiar mnemonic format on any 7000 series CRT. In this bus analyzer, a standard 7D01 Logic Analyzer acquires blocks of 256 bus “transactions” and a modified DF1 Display Formatter displays the data in GPIB format.

The bus analyzer can operate in either of two modes.

In one mode, the bus analyzer synchronously acquires information using the GPIB data valid (DAV) line as a clock. As many as 256 instructions are stored in the 7D01 and then disassembled and displayed on the DF1 in IEE-488 message mnemonics familiar to the GPIB user. The 7D01 uses 12 of the available 16 lines to monitor ATN, EOI, SRQ, REN and the eight data lines. The eight data lines are received on channels 8-15 with the clock line going to DAV. On the other probe, channel 4 goes to REN, 15 to SRQ, 6 to EOI, and 7 to ATN. Channels 0-3 make up four user-definable probes.

In the second mode, the user assigns three of the four remaining lines to the three-wire handshake, and then uses the internal clock (at an appropriate sampling rate) to study the timing relation of the three lines. For example, the designer could set up the word recognizer to trigger the 7D01 on any one of the ATN messages and then study the handshake lines for that message in the timing mode.

More details were given in the August 15, 1977 issue of Engineering News. Bruce Ableidinger wrote the GPIB disassembler code and Jeff Bradford, who wrote the original DF1 code, helped interface it to the DF1. The modified DF1 discussed here was announced as a product in January 1978.

Internals

An internal jumper allows the user to select the source of the on-screen readout in timing diagram mode, which can be either the mainframe readout supplied by the 7D01, or superimposed by the DF1/DF2. The latter is the standard setting and allows the DF1/DF2+7D01 combination to be used in mainframes without readout, e.g. the large-screen 7603N.

The DF1/DF2 has no direct connection to the scope mainframe − it attaches to the 7D01 through a 50-pin D-sub connector on the right side panel only. The DF1/DF2 and 7D01 are mechanically coupled by three nylon standoffs that slide into cutouts in the 7D01's case rails. The bottom two standoffs are fixed and are inserted first, then the connector is plugged in and the third, sliding, stand-off at the top is moved to its locked position.

The DF1/DF2 is built around a Motorola 6800 microprocessor with two (DF2: three) 2K×8 masked ROMs and sixteen 1K×1 SRAMs (Intel 2102).

The DF1, DF2 and 7D01 are often affected by bad TI IC sockets and/or ROM failures, see the Repairs tab.

Memory map

Address (hex)	Use
0000-007F	Scratchpad RAM (U274, Motorola 6810A)
0080-00FF	I/O registers
4000-47FF	ROM U820 on DF2 expansion board (156-1132-00, 2k×8, 6831B)
4800-4FFF	ROM socket on DF2 expansion board, unused
5000-57FF	ROM socket on DF2 expansion board, unused
5800-5FFF	ROM socket on DF2 expansion board, unused
6000-63FF	1KB RAM
8000-63FF	1KB display RAM, "write-only"
Axxx	Vertical map address register (→ U552, U554)
Cxxx	Horizontal map address register (→ U452, U454)
F000-F7FF	ROM U294 (156-0900-00, 2k×8, GI RO-3-8316 or Mostek MK31000)
F800-FFFF	ROM U284 (156-0899-00, 2k×8, GI RO-3-8316 or Mostek MK31000)

Pictures

DF1

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  DF1 front panel

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  7D01 and DF1 in 7313

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  DF1 internal, right side

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  DF1 internal, left side, ROM chips removed from sockets

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  DF1 internal, left side, with ROM replacement piggyback board (prototype)

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  ROM replacement piggyback board (production)

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  DF1 front with faceplate removed, showing keyboard PCB. Note three unpopulated key positions.

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  Side connector

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DF2

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  DF2 front panel

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  103-0209-00 GPIB probe

Displays

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  Timing diagram with mainframe readout

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  Timing diagram with DF readout

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  Timing diagram zoomed

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  Map diagram with octal cursor-position readout

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  Map diagram with binary cursor-position readout

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  Octal state table without reference

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  Binary state table with reference

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  DF2 GPIB table (random data)

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  DF2 ASCII table (16 bit mode in 2 columns). Note lowercase character "o" is displayed as <O>.

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  7D01 + DF1/DF2 Timing Diagram (with DF1/DF2 readout)

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  7D01 + DF1/DF2 State Table example - 8 bit mode, 7D01 table left with highlighted differences to DF1/DF2 reference table on the right