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P6230: Difference between revisions
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The P6230 acts as a standard 500 Ω passive voltage probe with the additional capability of having an adjustable tip "nulling voltage." This feature reduces the dc-loading effects on the probe when it is used to measure signals whose mid-voltage value is other than zero volts, or in circuits where the termination impedance is returned to other than ground level. The Input Bias/Offset Voltage may be adjusted so that at a particular test-signal voltage both ends of the probe input-resistor are at equal potentials and no current is flowing through the resistor. | The P6230 acts as a standard 500 Ω passive voltage probe with the additional capability of having an adjustable tip "nulling voltage." This feature reduces the dc-loading effects on the probe when it is used to measure signals whose mid-voltage value is other than zero volts, or in circuits where the termination impedance is returned to other than ground level. The Input Bias/Offset Voltage may be adjusted so that at a particular test-signal voltage both ends of the probe input-resistor are at equal potentials and no current is flowing through the resistor. | ||
ECL logic is most commonly operated from a −5.2 V supply with V<sub>CC</sub> connected to ground. The output of an ECL gate is the emitter of an NPN emitter follower stage. The output is pulled down to a negative supply (about −2 V) with an external resistor (50 Ω to 100 Ω). Since speed is a major consideration in ECL designs, the interconnections between gates are often transmission lines, and the pull-down resistor doubles as a line termination. | |||
ECL logic is most commonly operated from a −5.2 V supply with | |||
If a standard 500 Ω, 10× probe without the input Bias/Offset feature were used to examine an ECL output, the probe's 500 Ω resistance to ground would form a voltage divider with the gate's output-termination resistor. This divider can cause distortion of the output signal levels, shift the DC operation point of the output transistor, and reduce the gate's noise margin. | If a standard 500 Ω, 10× probe without the input Bias/Offset feature were used to examine an ECL output, the probe's 500 Ω resistance to ground would form a voltage divider with the gate's output-termination resistor. This divider can cause distortion of the output signal levels, shift the DC operation point of the output transistor, and reduce the gate's noise margin. | ||
The DC-load nulling capability of the P6230 helps to solve this problem. By adjusting the Input Bias/Offset Voltage to the ECL low level or to the termination voltage, the only effect of the probe resistance will be a small decrease in the ECL output-termination resistance. The effect of the probe on output voltage levels is negligible. | The DC-load nulling capability of the P6230 helps to solve this problem. By adjusting the Input Bias/Offset Voltage to the ECL low level or to the termination voltage, the only effect of the probe resistance will be a small decrease in the ECL output-termination resistance. The effect of the probe on output voltage levels is negligible. | ||
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