39,721
edits
7D01: Difference between revisions
no edit summary
No edit summary |
No edit summary |
||
| Line 15: | Line 15: | ||
<small> | <small> | ||
'''Alternate copies''' | '''Alternate copies''' | ||
* [https://w140.com/smb/7d01_sm.pdf 7D01 Instruction Manual, revised Oct 1982, part no 070-2206-02 (OCR | * [https://w140.com/smb/7d01_sm.pdf 7D01 Instruction Manual, revised Oct 1982, part no 070-2206-02] (OCR) | ||
'''Brochures''' | '''Brochures''' | ||
* [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976 | * [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976]] | ||
</small> | </small> | ||
}} | }} | ||
| Line 27: | Line 27: | ||
The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier . | The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier . | ||
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to | The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V. | ||
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock. | The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock. | ||