7B92: Difference between revisions

{{Plugin Sidebar

|manufacturer=Tektronix

|type=7B92  

|summary=500 MHz Dual Timebase  

|image=7b92a-front.jpg  

|caption=7B92A front  

|introduced=1971  

|discontinued=1992  

|series=7000-series scopes

|designers=Bill DeVey;Les Larson;Val Garuts

|manuals=

The '''Tektronix 7B92''' is a 500 MHz dual timebase plug-in for [[7000-series scopes]].  

It was introduced along with the [[7904]] mainframe in 1972.  In 1976, it was updated as the 7B92A.

An "HF Sync" triggering mode is provided in which the trigger level control varies the frequency of a built-in oscillator to lock on to the input for input signals from 100 to 500 MHz, providing higher sensitivity than the direct trigger (which is specified up to 500 MHz as well).

Internal jumpers are provided to configure the 7B92 for operation in 7800/7900 vs. slower mainframes, and to select whether the variable control affects the delaying or the delayed time base.

As a dual time base, the 7B92 uses the top field in the [[7000 series readout system|display readout]] for the sweep speed of the main and the bottom field for the delayed time base.   

The delay time can only be read from the 10-turn analog dial.

The 7B92 has no magnifier function but its regular sweep dial setting reaches down to 500 ps/Div.  It has no provision for X-Y operation.

The 7B92 uses a discrete trigger circuit containing [[152-0177-02]] [[tunnel diodes]]. Up to serial number B069999, the 7B92A used a trigger circuit with [[155-0061-00]] amplifiers and [[152-0177-02]] tunnel diodes. After that, the 7B92A used a [[155-0061-00]] trigger amplifier followed by a [[155-0150-00]] trigger detector.

The 7B92A uses one other custom IC, the [[155-0049-00|155-0049-xx]] sweep control circuit. The internal jumper for mainframe selection (7800/7900/7100 vs. slower) actually increases the minimum holdoff time on the slower mainframe selection by adding a 214pF capacitor (C307 for 7B92, C835 for 7B92A) to pin 8 of the sweep control IC [[155-0049-00|155-0049-xx]] in parallel to the existing capacitors. This increases the minimum pulse width of the holdoff signal on [[7000_Series_plug-in_interface|pin B4]] so that the sweep logic of slower mainframes can handle it properly. The effect of this jumper is only noticeable for sweep speeds of 20 μs/Div. and faster, since there the smallest shunt capacitance is used on pin 8, and the holdoff time is minimal.

Tek 7b92 front.jpg    | 7B92 front

Tek 7b92 right.jpg    | 7B92 right

Tek 7b92 left.jpg    | 7B92 left

7b92a-front.jpg      | 7B92A front

Tek 7b92a right.jpg  | 7B92A right

Tek 7b92a left.jpg    | 7B92A left

Tek 7b92a block.png  | 7B92A block diagram

7b92a-triggering-974mhz.jpg  | A 7B92A (B098xxx) triggering a 974 MHz sine applied to a [[7904]] mainframe via a 067-0587-02 calibration fixture (maximum triggerable frequency for this specimen).

Tek7904-7a19-7b92a-1010mhz-hfsync.jpg | A 7B92A (B098xxx) displaying a 1.01 GHz sine in HF Sync mode on a [[7904]] mainframe via a [[7A19]] amplifier (maximum signal generator frequency).