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|series=7000-series scopes
|series=7000-series scopes
|type=7D01  
|type=7D01  
|summary=Logic Analyzer  
|summary=16-ch Logic Analyzer  
|image=Tek 7D01 Front 2.jpg  
|image=Tek 7D01 Front 2.jpg  
|caption=Tektronix 7D01 without display formatter  
|caption=Tektronix 7D01 without display formatter  
|introduced=1976  
|introduced=1976  
|discontinued=1985
|discontinued=1985
|designers=Murlan Kaufman;Keith Taylor;Morris Green;Jeff Bradford;Ed Wolf;Vendell Damm
|manuals=
|manuals=
* [[Media:070-2205-02.pdf|7D01 Operators Manual]] (OCR)
* [[Media:070-2205-02.pdf|7D01 Operators Manual]] (OCR)
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<small>
<small>
'''Alternate copies'''
'''Alternate copies'''
* [https://w140.com/smb/7d01_sm.pdf 7D01 Instruction Manual, revised Oct 1982, part no 070-2206-02] (OCR)
* [[Media:070-2206-02_2.pdf|7D01 Instruction Manual 070-2206-02 rev. Oct 1982]] (OCR)
 
'''Brochures'''
'''Brochures'''
* [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976]]
* [[Media:Logic Analyzers Brochure 1976.pdf|Tektronix Logic Analyzers Brochure 1976]]
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When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen [[7603N]].
When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen [[7603N]].


The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier.
Project manager for the 7D01 was [[Murlan Kaufman]].  Project leader was [[Keith Taylor]], with [[Morris Green]] and [[Jeff Bradford]] doing electrical design, and [[Ed Wolf]] mechanical design. [[Wendell Damm]] worked on the active probe.
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
 
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs.   
The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
 
There is no internal glitch detector, but a separate [[DL2]] or [[DL502]] latch plug-in can be used to stretch short pulses ≥5 ns to the clock period.
The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.  
 
Project manager for the 7D01 was [[Murlan Kaufman]].


{{BeginSpecs}}
{{BeginSpecs}}
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}}
}}
{{EndSpecs}}
{{EndSpecs}}
==Links==
* [https://paulcarbone.com/blog/tekronix-7d01-logic-analyzer/ 7D01 @ paulcarbone.com] (with detailed photos)
* [https://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/logicanalyzer_7D01.htm 7D01 @ amplifier.cd]
* [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com]
{{Documents|Link=7D01}}
==Acquisition==
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier.
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. 
The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
There is no internal glitch detector, but a separate [[DL2]] or [[DL502]] latch plug-in can be used to stretch short pulses ≥5 ns to the clock period.
The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.


==Internals==
==Internals==
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The 7D01 is often affected by [[bad TI IC sockets]], see [[7D01/Repairs|the Repairs tab]].
The 7D01 is often affected by [[bad TI IC sockets]], see [[7D01/Repairs|the Repairs tab]].
==Links==
* [https://w140.com/tekscope_1976vol8no2_7d01.pdf 7D01 Article in 1976 Volume 8 Number 2 Tekscope (PDF)]
* [https://paulcarbone.com/blog/tekronix-7d01-logic-analyzer/ 7D01 @ paulcarbone.com] (with detailed photos)
* [http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_7000_series_special/logicanalyzer_7D01.htm 7D01 @ amplifier.cd]
* [http://www.barrytech.com/tektronix/tek7000/tek7d01-df1.html 7D01 @ barrytech.com]


==Pictures==
==Pictures==
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Tek_7D01_Memory.jpg      | 7D01 Memory Board
Tek_7D01_Memory.jpg      | 7D01 Memory Board
Tek_7D01_timing.jpg      | Standalone 7D01 Timing Diagram (using mainframe readout)
Tek_7D01_timing.jpg      | Standalone 7D01 Timing Diagram (using mainframe readout)
Tek_7D01-DF01_timing.jpg  | 7D01 + [[DF1]] (or [[DF2]]) Timing Diagram
Tek_7D01-DF01_timing.jpg  | 7D01 + [[DF1]]/DF2 Timing Diagram (readout from DF)
Tek_7D01-DF01_table.jpg  | 7D01 + [[DF1]] (or [[DF2]]) State Table
Tek_7D01-DF01_table.jpg  | 7D01 + [[DF1]]/DF2 State Table
</gallery>
</gallery>


{{Custom ICs|7D01}}
==Components==
{{Parts|7D01}}


[[Category:7000 series special-function plugins]]
[[Category:7000 series special-function plugins]]
[[Category:Logic analyzers]]
[[Category:7000 series logic analyzer plugins]]
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