ACVS: Difference between revisions

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→‎ACVS in 11000-Series Mainframes

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 == ACVS in 11000-Series Mainframes ==
-In the 11300 mainframes, the ACVS is controlled by an 8051-family microcontroller.
+In 11300 mainframes, the ACVS is controlled by an 8051-family microcontroller.
 It employs a [[Media:DAC312.pdf|DAC312]] 12-bit DAC,
-whose output is fed to an array of 28 sample-and-hold circuits similar to the ones in the plug-ins.
+whose output is fed to an array of 32 sample-and-hold circuits similar to the ones in the plug-ins.
 A refresh cycle sequentially refreshes the voltage on each of the sample-and-hold capacitors.
 The time to complete the entire refresh cycle is 900 μs.
-The precision is 12 bits for all but two of the analog outputs.
+The precision of each sample-and-hold voltage 12 bits.
-On those two, the precisions is 14.6 bits.
+of the sample-and-hold voltages are used independently.
-These high-precision outputs are formed by combining three 12-bit outputs using resistor summing networks.
+Six of the voltages are combined in groups of three, using resistor summing networks,
+to produce two outputs that each have 14.6 bit precision.
+These two precision voltages are DLYREF0 and DLYREF1,
+which are compared with the sweep ramp to generate sweep delay pulse.
+In earlier analog scopes (e.g., the [[565]]),
+the precision DC control voltage for the delay ramp comparator
+was produced by a multi-turn potentiometer on the front panel.
 <gallery>
 Tek 11300 acvs.png|ACVS schematic in 11300 mainframes
+Tek 11300 dlyref3.png|The weighted sum of three ACVS voltages is fed to the delay ramp comparator
 </gallery>
 [[Category:Circuits and Concepts]]