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DL502: Difference between revisions
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{{TM500 | mfg=Tektronix | type=DL502 | function=digital latch| class=digital function | image=Tek dl502 1.JPG | introduced=1978 | discontinued=1984 | | |||
designers= |manuals= | |||
* [[Media:070-2397-00.pdf|Tektronix DL502 Manual (PDF)]] | |||
* [http://w140.com/DD501-DL502-WR501.pdf Catalog Descriptions of DD501, DL502, and WR501 (PDF)] | * [http://w140.com/DD501-DL502-WR501.pdf Catalog Descriptions of DD501, DL502, and WR501 (PDF)] | ||
}} | |||
It is used with the [[7D01]] or [[LA501W]] logic analyzers to detect narrow pulses in a data stream that cannot be detected by the logic analyzer alone. | |||
The DL502 has two inputs for [[P6451]] 8+1 channel probes and two output cables with the same connectors as the probes, to plug into the 7D01's inputs. Additionally the "Store Clock Out" connector of the [[7D01]] needs to be connected to the "Store Clock In" connector of the DL502. | |||
When paired with a [[LA501W]] the output connectors plug into the [[WR501]] that is part of the [[LA501W]] bundle. The [[LA501W]] must be modified with the [[012-0725-01|LA501W Clock Access Conversion Kit]] to provide the necessary clock for the "Store Clock In" connector of the DL502. | |||
{{BeginSpecs}} | |||
{{Spec |Number of channels | 16}} | |||
{{Spec |Minimum pulse width | 5ns}} | |||
{{Spec |Minimum clock period | 20ns}} | |||
{{EndSpecs}} | |||
==Links== | |||
{{Documents|Link=DL502}} | |||
==Pictures== | |||
<gallery> | <gallery> | ||
Tek dl502 1.JPG | |||
DL502_catalog.jpg |catalog image | |||
Dl502 description.png|description | |||
</gallery> | </gallery> | ||