32,948
edits
11301: Difference between revisions
Jump to navigation
Jump to search
→Internals
No edit summary |
|||
| Line 61: | Line 61: | ||
On the mainframe side, this communication is controlled by the U1760 SDI chip on the A11 Main Processor board | On the mainframe side, this communication is controlled by the U1760 SDI chip on the A11 Main Processor board | ||
(the top rear board). | (the top rear board). | ||
The 11301 SDI is a synchronous serial interface. | |||
The clock signal, which is generated by the mainframe, | |||
is 5V TTL, 4 MHz, constantly running. | |||
==Pictures== | ==Pictures== | ||