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11301: Difference between revisions
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==Internals== | ==Internals Common to the 11301 and 11302 == | ||
The | In this section, "11300" refers to the 11301 and 11302. | ||
Like a typical analog scope, the | |||
The 11300 is a digitally controlled analog oscilloscope. | |||
Like a typical analog scope, the 11300 has vertical amplifiers, a trigger circuit, | |||
a timebase/sweep, a horizontal amplifier, and a CRT. | a timebase/sweep, a horizontal amplifier, and a CRT. | ||
Unlike traditional analog scopes, the | Unlike traditional analog scopes, the 11300 contains a significant amount of digital circuitry, | ||
including multiple microprocessors. | including multiple microprocessors. | ||
The digital circuitry provides several externally-observable features: | The digital circuitry provides several externally-observable features: | ||
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e.g., the trigger holdoff is implemented with a counter instead of with a multivibrator. | e.g., the trigger holdoff is implemented with a counter instead of with a multivibrator. | ||
There are many DAC-generated analog control voltages in the | There are many DAC-generated analog control voltages in the 11300. | ||
The left and center plug-in can be used as the vertical axis and/or the trigger signal. | The left and center plug-in can be used as the vertical axis and/or the trigger signal. | ||
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The clock signal, which is generated by the mainframe, | The clock signal, which is generated by the mainframe, | ||
is 5V TTL, 4 MHz, constantly running. | is 5V TTL, 4 MHz, constantly running. | ||
The 11300 performs a variety of self-checks and self-calibration. | |||
Some of the self-checks are digital in nature, e.g., testing RAM by writing | |||
a pattern, reading it back, and comparing what was read with what was written. | |||
Other tests are analog in nature. | |||
For the analog tests, there is an analog bus, ABUS, | |||
that allows various voltages throughout the scope | |||
to be measured by the test routine. | |||
The ABUS is a fan-in tree formed by 74HC4051 analog multiplexers. | |||
One level of multiplexing happens at the module level. | |||
The ABUS signals from each of the modules are brought to the main ABUS multiplexer | |||
(lower left corner of schematic drawing 12, Partial A11 Main Processor Board). | |||
The output of the main ABUS multiplexer is fed to an LF398 sample and hold IC, | |||
the output of which is fed to an AD574 12-bit successive approximation analog to digital converter. | |||
==Pictures== | ==Pictures== | ||