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|introduced=1984 | |introduced=1984 | ||
|discontinued=1990 | |discontinued=1990 | ||
|designers=Kirk Wimmer | |||
|manuals= | |manuals= | ||
* [[Media:070-4285-00.pdf|7A42 Operator Manual]] (OCR) | * [[Media:070-4285-00.pdf|7A42 Operator Manual]] (OCR) | ||
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** [[Media:070-4286-00.pdf|070-4286-00 Volume 1]] (OCR) | ** [[Media:070-4286-00.pdf|070-4286-00 Volume 1]] (OCR) | ||
** [[Media:070-4654-00.pdf|070-4654-00 Volume 2, Signature Analysis Tables]] (OCR) | ** [[Media:070-4654-00.pdf|070-4654-00 Volume 2, Signature Analysis Tables]] (OCR) | ||
{{ROM Images}} | |||
}} | }} | ||
The '''Tektronix 7A42''' is a four-channel 350 MHz plug-in for [[7000-series scopes]]. It is a double-wide plug-in, | The '''Tektronix 7A42''' is a four-channel 350 MHz plug-in for [[7000-series scopes]]. It is a double-wide plug-in, designed by [[Kirk Wimmer]]. | ||
'''Vertical:''' | |||
A fifth trace, "Trigger View", displays the trigger function output or external clock input. | :The 7A42 was specifically designed for logic signals (TTL, ECL, CMOS). It is not a Logic Analyzer however – the signal path and display is analog. | ||
:The input V/div setting can only be seen in the mainframe's readout, and adapts automatically when a [[BNC connector with readout ring|pin-coded ×10 probe]] is attached. (×100 probes are not supported and are incorrectly recognized as ×10.) | |||
:A fifth trace, "Trigger View", displays the trigger function output or external clock input. | |||
'''Triggering:''' | |||
The trigger can be qualified by an external clock. A trigger filter control, variable from 0-300 ns, allows events shorter than the selected length to be suppressed. A TTL-level "reset" input will inhibit the trigger | :The 7A42 supports triggering based on Boolean conditions of the four inputs. | ||
:The trigger can be qualified by an external clock. A trigger filter control, variable from 0-300 ns, allows events shorter than the selected length to be suppressed. A TTL-level "reset" input will inhibit the trigger when active. | |||
:There are two sets of trigger conditions, A and B, that can be individually selected or paired in an "A then B" mode called ''nested triggering'', where the occurrence of condition A arms the trigger and condition B causes the trigger to be generated. | |||
:The "A then B" interval gate signal can be routed to a counter for time measurement or event counting. | |||
:Selected by an internal jumper, the front-panel trigger output can be configured for either the trigger signal, or the "A then B" interval | |||
:The trigger level is set digitally for each channel, and shown on a 7-segment display. The trigger level display can also be used as a DVM to measure the offset voltage to which which an attached [[P6230]] probe is set. | |||
The [[ | '''Mainframe Interface:''' | ||
:Signal/Trigger outputs and mainframe readout use the left slot, allowing the 7A42 to be installed in the two center bays in a four-bay mainframe, together with another vertical plug-in in the left vertical bay. | |||
:The right slot additionally provides the "A then B" interval gate on the trigger lines. | |||
:There is a jumper to allow the readout to work in a [[7854]] mainframe. | |||
'''Probes:''' | |||
:Tektronix recommended the [[P6131]], 300 MHz, 10 MΩ ×10 probe, and the [[P6230]], 1.5 GHz, 450/50 Ω ×10, variable-offset probe for ECL circuits. | |||
{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Bandwidth | 350 MHz}} | {{Spec | Bandwidth | 350 MHz in [[7104]], 300 MHz in [[7904]] }} | ||
{{Spec | Deflection | | {{Spec | Deflection | | ||
* 0.1 | * TTL mode: 0.1, 0.2 or 0.5 V/div ; 1, 2 or 5 V/div with ×10 probe | ||
* 20 | * ECL mode: 20, 50 or 100 mV/div ; 0.2, 0.5 or 1 V/div with ×10 probe | ||
* always DC coupled | |||
{{Spec | Input impedance | 1 MΩ // 15 pF or 50 Ω}} | }} | ||
{{Spec | Input impedance | 1 MΩ // 15 pF or 50 Ω }} | |||
{{Spec | Max. input voltage | | {{Spec | Max. input voltage | | ||
* at 1 MΩ: 25 V (DC+peak AC) below 36 MHz, down to 3 V<sub>AC</sub> at 300 MHz | * at 1 MΩ: 25 V (DC+peak AC) below 36 MHz, down to 3 V<sub>AC</sub> at 300 MHz | ||
* at 50 Ω: 5 V<sub>RMS</sub> during any 1 ms interval}} | * at 50 Ω: 5 V<sub>RMS</sub> during any 1 ms interval}} | ||
{{Spec | Trigger level | | {{Spec | Trigger level | | ||
* −1.27 to +1.28 V (TTL | * TTL Mode ×1: −1.27 to +1.28 V in 10 mV steps (Preset: 0.14 V) | ||
* | * TTL Mode ×10: −12.7 to +12.8 V in 100 mV steps (Preset: 1.4 V) | ||
{{Spec | Hysteresis | 40 mV (TTL), 8 mV (ECL | * ECL Mode ×1: −0.254 V to +0.256 V in 2 mV steps (Preset: –0.13 V) | ||
* ECL Mode ×10: −2.54 V to +2.56 V in 2 mV steps (Preset: –1.3 V) | |||
}} | |||
{{Spec | Trigger Hysteresis | 40/400 mV (TTL), 8/80 mV (ECL) }} | |||
{{Spec | Features | | {{Spec | Features | | ||
* NiCd battery to preserve front-panel control status}} | * NiCd battery to preserve front-panel control status}} | ||
{{Spec | Weight | 2.8 kg / 6.2 lb}} | {{Spec | Weight | 2.8 kg / 6.2 lb}} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
==Links== | |||
The [[067-1155-99]] calibration fixture is specific to the 7A42. | |||
{{Documents|Link=7A42}} | |||
{{PatentLinks|7A42}} | |||
==See also== | |||
* [[067-1155-99]] | |||
* [[A6701]] | |||
* [[821]] | |||
==Internals== | ==Internals== | ||
The 7A42's functions are controlled by an [[Intel 8085]]A microprocessor, with code in three 2764 EPROMs (a fourth ROM socket is unused). The front-panel pushbuttons are handled by an Intel 8279 keyboard controller. | The 7A42's functions are controlled by an [[Intel 8085]]A microprocessor, with code in three 2764 EPROMs (a fourth ROM socket is unused). The front-panel pushbuttons are handled by an [[Intel 8279]] keyboard controller. | ||
Each of the four input attenuator | Each of the four [[119-1517-00]] input attenuator modules contains five [[148-0145-00|148-0145-00 miniature bi-stable relay actuators]]. These have four long pins plugging in to the base board, driving two solenoids that move a yoke which is held in the last active position by a permanent magnet. The yoke moves a pair of contact springs that directly short corresponding pads on the thick-film ceramic substrate. The relay coils are wired in a 4×5 matrix. | ||
The 7A42 contains its own switch mode PSU, based on an SG3524 controller, that generates +5 V, −2 V and −5 V from the mainframe's ±50 V rails. | The 7A42 contains its own switch-mode PSU, based on an [[SG3524]] controller, that generates +5 V, −2 V and −5 V from the mainframe's ±50 V rails. | ||
There is a [[7A42/Repairs|NiCd backup battery]] that allows the unit to retain its last configuration. | There is a [[7A42/Repairs|NiCd backup battery]] that allows the unit to retain its last configuration. | ||
Line 68: | Line 87: | ||
A 555 timer implements a 15 ms "real-time clock" and watchdog reset, another drives a beeper. | A 555 timer implements a 15 ms "real-time clock" and watchdog reset, another drives a beeper. | ||
An internal jumper enables partial compatibility with a [[7854]] mainframe in storage mode (displaying any single channel, 1+2 in ALT, or 3+4 in ALT only). There are no restrictions with the 7854 in analog mode. | |||
==Pictures== | ==Pictures== | ||
Line 87: | Line 103: | ||
Tek 7a42 fr6.jpg | 7A42 rear view | Tek 7a42 fr6.jpg | 7A42 rear view | ||
Tek 7a42 fr7.jpg | 7A42 top view | Tek 7a42 fr7.jpg | 7A42 top view | ||
Tek-7A42-Bus.jpg | Schematic cartoon: Bus | |||
Tek-7A42-Chirp.jpg | Schematic cartoon: Chirp | |||
</gallery> | </gallery> | ||
'''Internal''' | '''Internal''' | ||
<gallery> | <gallery> | ||
7A42 amplifier board.jpg | amplifier board (one attenuator cover removed) | |||
Tek 7a42 fr11.jpg | amplifier board front - attenuators, amplifiers, channel switches | |||
Tek 7a42 fr12.jpg | amplifier board rear - channel switches, two 15 ns delay lines | |||
Tek 7a42 fr11.jpg | amplifier board front - attenuators, amplifiers, channel switches | 7A42 attenuator 1.jpg | attenuator, cover removed | ||
Tek 7a42 fr12.jpg | amplifier board rear - channel switches, two 15 ns delay lines | 7A42 attenuator cover.jpg | attenuator cover | ||
7A42 attenuator 2.jpg | attenuator, top | |||
7A42 attenuator 3.jpg | attenuator, one relay actuator removed | |||
7A42 attenuator 4.jpg | attenuator, all relay actuators removed | |||
7A42 attenuator 5.jpg | attenuator, all relay actuators removed | |||
Tek 7a42 fr10.jpg | microprocessor board | |||
Tek 7a42 fr8.jpg | memory backup battery on microprocessor board replaced with LiIon | |||
Tek 7a42 fr9.jpg | internal switch mode PSU for digital logic supplies | |||
Tek 7a42 13.jpg | Tek 7a42 13.jpg | ||
Tek 7a42 14.jpg | Tek 7a42 14.jpg |