7A42: Difference between revisions

7A42 (view source)

45 bytes added , 23 December 2019

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 * 20 / 50 / 100 mV/Div (ECL mode)
 * each direct or through 10:1 probe}}
-{{Spec | Input impedance | 1MΩ or 50 Ω}}
+{{Spec | Input impedance | 1 MΩ or 50 Ω}}
 {{Spec | Max. input voltage |
-* at 1 MΩ: 25 V DC+peak AC below 36 MHz, down to 3 V AC at 300 MHz
+* at 1 MΩ: 25 V (DC+peak AC) below 36 MHz, down to 3 V<sub>AC</sub> at 300 MHz
-* at 50Ω: 5 V RMS during any 1 ms interval}}
+* at 50 Ω: 5 V<sub>RMS</sub> during any 1 ms interval}}
 {{Spec | Trigger level |
-* -1.27 to +1.28 V (TTL mode) in 10 mV steps
+* −1.27 to +1.28 V (TTL mode) in 10 mV steps
-* -254 mV to +256 mV (ECL mode) in 2 mV steps (or ×10)}}
+* −254 mV to +256 mV (ECL mode) in 2 mV steps (or ×10)}}
 {{Spec | Hysteresis | 40 mV (TTL), 8 mV (ECL) (or ×10)}}
 {{Spec | Features |
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 ==Internals==
-The 7A42's functions are controlled by an 8085A microprocessor.
+The 7A42's functions are controlled by an [[Intel 8085]]A microprocessor.
 Each of the four input attenuator circuits contains five [[miniature relays]]. The bistable relay coils are wired in a 4x5 matrix.
-The 7A42 contains its own switch mode PSU, based on an SG3524 controller, that generates +5 V, -2 V and -5 V from the mainframe's +/-50 V rails.
+The 7A42 contains its own switch mode PSU, based on an SG3524 controller, that generates +5 V, −2 V and −5 V from the mainframe's ±50 V rails.
 ==See Also==