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067-0587-02: Difference between revisions
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Internal signals are derived from a 1 MHz oscillator with selectable decade divisions down to 10 Hz repetition. | Internal signals are derived from a 1 MHz oscillator with selectable decade divisions down to 10 Hz repetition. | ||
The clock is delayed, amplified and limited, then fed to a | The clock is delayed, amplified and limited, then fed to a Schottky-diode based pulse shaper with L-C compensating networks. The output pulse has a rise time of max. 150 picoseconds with less than 2% aberrations. | ||
The staircase generator for Gain mode is implemented using a 4 bit count and multiplexer. The 0-volt step (No. 6) is held for five counts, producing a brighter trace to allow easy alignment wit the center of the screen. | The staircase generator for Gain mode is implemented using a 4 bit count and multiplexer. The 0-volt step (No. 6) is held for five counts, producing a brighter trace to allow easy alignment wit the center of the screen. | ||