11401: Difference between revisions

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* [[Category:Manual needed]] ''please add service manual''
* [[Category:Manual needed]] ''please add service manual''
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The '''Tektronix 11401''' is a digitizing scope with three plugins accepting [[:Category:11000 series plugins|11000-series plugins]] and [[7000-series plug-ins]].
The '''Tektronix 11401''' is a digitizing scope with three plugin bays accepting [[:Category:11000 series plugins|11000-series plugins]] and [[7000-series plug-ins]].
 
Project manager of the 11400 series was [[Tom Rousseau]], who was also project manager for the [[7854]].
The 11400 engineering team included some of the main people from the 7854 project.


<!-- Using random equivalent time sampling, it can acquire up to eight channels at 300 MHz, six channels at 600 MHz, or up to 3 channels at 1 GHz. -->
<!-- Using random equivalent time sampling, it can acquire up to eight channels at 300 MHz, six channels at 600 MHz, or up to 3 channels at 1 GHz. -->
The 11401 mainframe uses equivalent time sampling at a rate of 20MHz (20Msps).
The 11401 mainframe uses equivalent time sampling at a rate of 20 MHz (20 Msps).
Each sample has 10 bits of resolution.
Each sample has 10 bits of resolution.
It is capable of displaying eight separate 10 bit resolution traces at one time.
It is capable of displaying eight separate 10 bit resolution traces at one time.
The mainframe is fully remotely programmable over RS-232 or GPIB.  
The mainframe is fully remotely programmable over [[RS-232]] or [[GPIB]].


This mainframe accepts up to three plugins with differing numbers of channels and bandwidths.
This mainframe accepts up to three plugins with differing numbers of channels and bandwidths.
For example, each [[11A52]] plugin allows two inputs at 500MHz bandwidth (50 ohm only input impedance).
For example, each [[11A52]] plugin allows two inputs at 500 MHz bandwidth (50 Ω only input impedance).
The [[11A34]] plugin allows four inputs at 300MHz bandwidth, and the [[11A32]] allows two channels at 300MHz.
The [[11A34]] plugin allows four inputs at 300 MHz bandwidth, and the [[11A32]] allows two channels at 300 MHz.
Three 11A34 plugins then allow up to 12 channels of information,
Three 11A34 plugins then allow up to 12 channels of information,
but the mainframe limits the number displayed at any one time to eight.
but the mainframe limits the number displayed at any one time to eight.
The other four channels may still be used for triggering.
The other four channels may still be used for triggering.
The [[11402]] and (later) [[11403]] and [[DSA600]] mainframes allow up to 1GHz of bandwidth
The [[11402]] and (later) [[11403]] and [[DSA600]] mainframes allow up to 1 GHz of bandwidth
with an [[11A71]] (one 50 ohm input) or two 50 ohm inputs in the (later) [[11A72]].
with an [[11A71]] with one 50 Ω input, or two 50 Ω inputs in the (later) [[11A72]].


{{MissingSpecs}}
Resolution is up to 10 ps horizontal and 10 bits vertical, with 10,240 points of memory.  
Resolution is up to 10 ps horizontal and 10 bits vertical, with 10,240 points of memory.  


==Internals ==
Note: The photos of the "Prototype 11401" are of a scope that said [[11331]] on the front panel.
Note: The photos of the "Prototype 11401" are of a scope that said [[11331]] on the front panel.
The project manager of the 11400 series was [[Tom Rousseau]], who was also project manager for the [[7854]].
The 11400 engineering team included some of the main people from the 7854 project.


The 11401 uses the [[156-2622-00]] [[SDI]] controller IC (U330).
The 11401 uses the [[156-2622-00]] [[SDI]] controller IC (U330).


== Vertical Signal Path ==
=== Vertical Signal Path ===
Each of the three plug-in bays in the 11401 has a dedicated sampler.
Each of the three plug-in bays in the 11401 has a dedicated sampler.
The sampling clock is common to the three samplers.
The sampling clock is common to the three samplers.
The sampling pulse is generated by an ECL 2-input OR gate being fed SAMPLE_CLOCK and delay_5ns(invert(SAMPLE_CLOCK)).
The sampling pulse is generated by an ECL 2-input OR gate being fed SAMPLE_CLOCK and delay_5ns(invert(SAMPLE_CLOCK)).
This produces 5ns pulses with rise time around 1 ns.
This produces 5 ns pulses with rise time around 1 ns, which are fed to a discrete NPN differential pair operating  
The 5 ns pulses are fed to a discrete NPN differential pair operating in a clipping current-switch mode,
in a clipping current-switch mode, resulting in faster edges.
resulting in faster edges.
The output of the differential pair drive a strobe generator IC, U1040, which is an M453 die,
The output of the differential pair drive a strobe generator IC, U1040, which is an M453 die,
packaged as part number [[155-0320-00]] or 155-0320-01, depending on the mainframe's serial number.
packaged as part number [[155-0320-00]] or 155-0320-01, depending on the mainframe's serial number.
U1040 has three sampling strobe outputs, which are fed to the sampling gates.
U1040 has three sampling strobe outputs, which are fed to the sampling gates.
The plug-in connector's differential "DISPLAY" pins are connected to the samplers by coaxial cable,  
The plug-in connector's differential "DISPLAY" pins are connected to the samplers by coaxial cable,  
i.e. there are no high-speed amplifiers in the mainframe's signal path.
i.e. there are no high-speed amplifiers in the mainframe's signal path.
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The contents of the RAM may have many points depending on the size of the acquisition window.
The contents of the RAM may have many points depending on the size of the acquisition window.
The "Waveform Compressor" board takes the contents of the acquisition RAM and renders it to 512 points on the horizontal axis for display.
The "Waveform Compressor" board takes the contents of the acquisition RAM and renders it to 512 points on the horizontal axis for display.
==Specifications==
[[Category:Specifications needed]] ''please add''


==Links==
==Links==
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[[Category:11000 series mainframes]]
[[Category:11000 series mainframes]]
[[Category:RS-232 interface]]
[[Category:GPIB interface]]