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7A42: Difference between revisions
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** [[Media:070-4286-00.pdf|070-4286-00 Volume 1]] (OCR) | ** [[Media:070-4286-00.pdf|070-4286-00 Volume 1]] (OCR) | ||
** [[Media:070-4654-00.pdf|070-4654-00 Volume 2, Signature Analysis Tables]] (OCR) | ** [[Media:070-4654-00.pdf|070-4654-00 Volume 2, Signature Analysis Tables]] (OCR) | ||
<small> | <small> | ||
'''ROM images''' | '''ROM images''' | ||
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The trigger can be qualified by an external clock. A trigger filter control, variable from 0-300 ns, allows events shorter than the selected length to be suppressed. A TTL-level "reset" input will inhibit the trigger if active. | The trigger can be qualified by an external clock. A trigger filter control, variable from 0-300 ns, allows events shorter than the selected length to be suppressed. A TTL-level "reset" input will inhibit the trigger if active. | ||
Selected by an internal jumper, either the trigger signal, or the "A then B" interval, is available on a front-panel trigger output. This can e.g. be routed a counter for time measurement or event counting. | Selected by an internal jumper, either the trigger signal, or the "A then B" interval, is available on a front-panel trigger output. This can e.g. be routed to a counter for time measurement or event counting. | ||
The input V/Div setting can only be seen in the mainframe's readout. There is a jumper to allow the readout to work in a [[7854]] mainframe. | The input V/Div setting can only be seen in the mainframe's readout. | ||
There is a jumper to allow the readout to work in a [[7854]] mainframe. | |||
The trigger level is set digitally and shown on a 7-segment display. | The trigger level is set digitally and shown on a 7-segment display. | ||
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{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Bandwidth | 350 MHz}} | {{Spec | Bandwidth | 350 MHz }} | ||
{{Spec | Deflection | | {{Spec | Deflection | | ||
* 0.1 / 0.2 / 0.5 V/Div (TTL mode) | * 0.1 / 0.2 / 0.5 V/Div (TTL mode) | ||
* 20 / 50 / 100 mV/Div (ECL mode) | * 20 / 50 / 100 mV/Div (ECL mode) | ||
* each direct or through 10:1 probe}} | * each direct or through 10:1 probe | ||
* always DC coupled }} | |||
{{Spec | Input impedance | 1 MΩ // 15 pF or 50 Ω}} | {{Spec | Input impedance | 1 MΩ // 15 pF or 50 Ω}} | ||
{{Spec | Max. input voltage | | {{Spec | Max. input voltage | | ||
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{{Spec | Weight | 2.8 kg / 6.2 lb}} | {{Spec | Weight | 2.8 kg / 6.2 lb}} | ||
{{EndSpecs}} | {{EndSpecs}} | ||
==Links== | |||
{{Documents|Link=7A42}} | |||
==See also== | |||
* [[067-1155-99]] | |||
* [[A6701]] | |||
* [[821]] | |||
==Internals== | ==Internals== | ||
The 7A42's functions are controlled by an [[Intel 8085]]A microprocessor, with code in three 2764 EPROMs (a fourth ROM socket is unused). The front-panel pushbuttons are handled by an Intel 8279 keyboard controller. | The 7A42's functions are controlled by an [[Intel 8085]]A microprocessor, with code in three 2764 EPROMs (a fourth ROM socket is unused). The front-panel pushbuttons are handled by an Intel 8279 keyboard controller. | ||
Each of the four input attenuator | Each of the four [[119-1517-00]] input attenuator modules contains five [[148-0145-00|148-0145-00 miniature bi-stable relay actuators]]. These have four long pins plugging in to the base board, driving two solenoids that move aa yoke which is held in the last active position by a permanent magnet. The yoke moves a pair of contact springs that directly short corresponding pads on the thick-film ceramic substrate. The relay coils are wired in a 4×5 matrix. | ||
The 7A42 contains its own switch mode PSU, based on an SG3524 controller, that generates +5 V, −2 V and −5 V from the mainframe's ±50 V rails. | The 7A42 contains its own switch mode PSU, based on an SG3524 controller, that generates +5 V, −2 V and −5 V from the mainframe's ±50 V rails. | ||
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A 555 timer implements a 15 ms "real-time clock" and watchdog reset, another drives a beeper. | A 555 timer implements a 15 ms "real-time clock" and watchdog reset, another drives a beeper. | ||
An internal jumper enables partial compatibility with a [[7854]] mainframe in storage mode (displaying any single channel, 1+2 in ALT, or 3+4 in ALT only). There are no restrictions with the 7854 in analog mode. | |||
==Pictures== | ==Pictures== | ||
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'''Internal''' | '''Internal''' | ||
<gallery> | <gallery> | ||
7A42 amplifier board.jpg | amplifier board (one attenuator cover removed) | |||
Tek 7a42 fr11.jpg | amplifier board front - attenuators, amplifiers, channel switches | |||
Tek 7a42 fr12.jpg | amplifier board rear - channel switches, two 15 ns delay lines | |||
Tek 7a42 fr11.jpg | amplifier board front - attenuators, amplifiers, channel switches | 7A42 attenuator 1.jpg | attenuator, cover removed | ||
Tek 7a42 fr12.jpg | amplifier board rear - channel switches, two 15 ns delay lines | 7A42 attenuator cover.jpg | attenuator cover | ||
7A42 attenuator 2.jpg | attenuator, top | |||
7A42 attenuator 3.jpg | attenuator, one relay actuator removed | |||
7A42 attenuator 4.jpg | attenuator, all relay actuators removed | |||
7A42 attenuator 5.jpg | attenuator, all relay actuators removed | |||
Tek 7a42 fr10.jpg | microprocessor board | |||
Tek 7a42 fr8.jpg | memory backup battery on microprocessor board replaced with LiIon | |||
Tek 7a42 fr9.jpg | internal switch mode PSU for digital logic supplies | |||
Tek 7a42 13.jpg | Tek 7a42 13.jpg | ||
Tek 7a42 14.jpg | Tek 7a42 14.jpg | ||