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| {{Plugin Sidebar |
| | #redirect [[DF1]] |
| manufacturer=Tektronix | type=DF2 |
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| summary=Display Formatter |
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| image=Tek df2.jpg |
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| caption=Tektronix DF2 |
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| introduced=1978|
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| discontinued=1985|
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| series=7D01|
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| manuals=
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| * [[Media:070-2478-00.pdf|Tektronix DF2 Manual]] (OCR)
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| {{ROM Images}}
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| * U284: [[Media:156-0899-00.bin|156-0899-00]] (2k×8, GI RO-3-8316 or [[Mostek MK31000]])
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| * U294: [[Media:156-0900-00.bin|156-0900-00]] (2k×8, GI RO-3-8316 or [[Mostek MK31000]])
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| * U820: [[Media:156-1132-00.bin|156-1132-00]] (2k×8, [[6831B]])
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| }}
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| The '''Tektronix DF2''' is a display formatter for use with the [[7D01]] logic analyzer.
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| It is a [[DF1]] with special support for debugging GPIB, from which it differs by having an extra front-panel "MENU" key and a daughter board with additional ROMs.
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| The DF2 does not, however, have a GPIB interface of its own − it can only analyze external GPIB traffic.
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| This functionality is invoked with the added MENU control (refer to the instruction manual for details).
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| Project manager for the DF2 was [[Murlan Kaufman]].
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| A [[103-0209-00|103-0209-00 GPIB to probe comb adapter]] was supplied with the DF2. This connects GPIB DIO1..DIO8 to CH8..CH15, DAV to the CLOCK input, ATN to CH7, EOI to CH6, SRQ to CH5, and REN to CH4. GPIB signals DAV, NRFD, NDAC and IFC brought out to pins on the connector. CH3..0 are user defined inputs that can track any of these signals, or others as needed. For GPIB analysis, bus data is acquired synchronously using the negative-going edge of the GPIB DAV (Data Valid) line as an external clock.
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| {{BeginSpecs}}
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| {{Spec | Memory | One reference table memory, same as 7D01 capacity (max. 16 channels at 254 bits/ch) }}
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| {{Spec | Display modes |
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| * State table: Hexadecimal, octal, or binary formats; two tables (reference, 7D01 memory) of 17 lines of 16-bit words
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| * Map: Dot display of the 16 data channels in X-Y coordinate points. Each dot location represents one possible combination of up to 16 inputs to the 7D01.
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| * GPIB: Displays 17 lines of decoded GPIB operations and/or ASCII data, and user-defined input signal states.
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| * ASCII: Displays 17 lines of decoded ASCII character along with its binary, octal, or hex value, in either 8– or 16–bit modes.
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| * Timing: Standard 7D01 display – 4, 8 or 16 bits
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| }}
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| {{Spec | Reset output | Positive 100 μs pulse, ≤0.4 V / ≥2.4 V }}
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| {{EndSpecs}}
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| ==Internals==
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| The DF1 is built around a [[Motorola 6800]] microprocessor with three 2K×8 masked ROMs (one on a ROM expansion board) and sixteen 1K×1 SRAMs (2101).
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| The DF2 and 7D01 are often affected by [[bad TI IC sockets]], see [[7D01/Repairs|the Repairs tab]].
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| ==Pictures==
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| <gallery>
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| Tek df2.jpg
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| Tek df2 7d01 lit.jpg
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| Tek_7D01-DF01_timing.jpg | 7D01 + [[DF1]] (or [[DF2]]) Timing Diagram
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| Tek_7D01-DF01_table.jpg | 7D01 + [[DF1]] (or [[DF2]]) State Table
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| </gallery>
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| {{Custom ICs|DF2}}
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| [[Category:7000 series special-function plugins]] | | [[Category:7000 series special-function plugins]] |
| [[Category:Logic analyzers]] | | [[Category:Logic analyzers]] |
| | [[Category:Introduced in 1978]] |