7S12: Difference between revisions

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96 bytes added ,  12 August 2014
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File:7s12-front.jpg | Front view without sampling head plug-ins
File:7s12-front.jpg | Front view without sampling head plug-ins
File:7s12-s6-s52-f.jpg | Front view with [[S-6]] sampling head and [[S-52]] pulse generator
File:7s12-s6-s52-f.jpg | Front view with [[S-6]] sampling head and [[S-52]] pulse generator
File:Tek 7s12.jpg |7S12 with [[S-53]] trigger recognizer in left bay (normally right)
File:7s12-s6-s52-7613.jpg | 7S12 TDR "self portrait" in [[7613]] storage mainframe
File:7s12-s6-s52-7613.jpg | 7S12 "self portrait" in [[7613]] storage mainframe
File:7s12-7s11-1ghz-store.jpg | 7S12 as a sampler, displaying a 1 GHz sine using a [[S-6]] sampling head and [[S-53]] trigger recognizer, 2<sup>nd</sup> channel (top) on a [[7S11]] with [[S-4]] sampling head.
File:7s12-7s11-1ghz-store.jpg | 7S12 as a sampler with 2nd channel on 7S11, S-4 and S-6 sampling heads, S-53 trigger recognizer displaying a 1 GHz sine.
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===Inside===
===Inside===
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File:7s12-5in.jpg | 7S12/S-6/S-52 displaying pulse reflection from ~ 5 in semi-rigid SMA cable. Stored display of two traces. Left trace: cable only, right trace: cable plus SMA-to-BNC adapter (~ 25 mm)  
File:7s12-5in.jpg | 7S12/S-6/S-52 displaying pulse reflection from ~ 5 in semi-rigid SMA cable. Stored display of two traces. Left trace: cable only, right trace: cable plus SMA-to-BNC adapter (~ 25 mm)  
File:7s12-reflected.jpg | 7S12/S-6/S-52 displaying reflected pulse from end of 5 in semi-rigid SMA cable. Stored display overlaying multiple traces, left to right: cable alone, SMA-to-BNC adapter added, BNC f-f adapter added, (cheap) 50 Ω terminator added.  
File:7s12-reflected.jpg | 7S12/S-6/S-52 displaying reflected pulse from end of 5 in semi-rigid SMA cable. Stored display overlaying multiple traces, left to right: cable alone, SMA-to-BNC adapter added, BNC f-f adapter added, (cheap) 50 Ω terminator added.  
File:7s12-7s11-1ghz-nonstore.jpg | 7S11+S-4 / 7S12+S-6+S-53 displaying a 1 GHz sine in normal mode wihout storage.
File:7s12-7s11-1ghz-nonstore.jpg | [[7S11]] with [[S-4]] and 7S12 with [[S-6]] and [[S-53]] displaying a 1 GHz sine in normal mode without storage. Sampling is evident.
File:7s12-7s11-1ghz-store2.jpg | 7S11+S-4 / 7S12+S-6+S-53 displaying a 1 GHz sine in normal mode wihout storage.
File:7s12-7s11-1ghz-store2.jpg | [[7S11]] with [[S-4]] and 7S12 with [[S-6]] and [[S-53]] displaying a 1 GHz sine in high-res mode with variable-persistence storage on a [[7613]].


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