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Pulses can be triggered by an external input, a manual trigger button, or an internal period generator (optionally gated by the trigger input). | |||
The trigger signal can be undelayed, delayed by a selectable time, or both (in which case double pulses are generated). | |||
The pulse duration, leading and trailing edge transition times, high- and low-level amplitude can be controlled independently. | |||
Period, delay, duration, and transition time switches each feature a custom position where a user-supplied internal capacitor determines the timing. | Period, delay, duration, and transition time switches each feature a custom position where a user-supplied internal capacitor determines the timing. | ||
{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec|Transition time| | {{Spec|Period|external, or internal <20 ns to >200 ms in 7 decade steps plus variable; ≥200 ms possible in custom range}} | ||
{{Spec|Output level|High and low levels adjustable independently in −20 V to +20 V range, limited to max. 20 V<sub>p-p</sub> (open circuit), 50 Ω source impedance (−10 V to +10 V into 50 Ω)}} | {{Spec|Jitter|<0.1% +50 ps }} | ||
{{Spec|Delay Time|<10 ns to >100 ms in 7 decade steps plus custom position and variable control; ≥100 ms possible in custom range}} | |||
{{Spec|Pulse Duration|square, or <10 ns to >100 ms in 7 decade steps plus custom position and variable control; ≥100 ms possible in custom range}} | |||
{{Spec|Transition time|Ranges 5 ns to 500 μs in decade steps plus custom position; separate ×1 to ×100 variable controls for leading and trailing edge (5 ns to 50 ms effective) }} | |||
{{Spec|Output level|High and low levels adjustable independently in −20 V to +20 V range, limited to max. 20 V<sub>p-p</sub> / min. 1 V<sub>p-p</sub> (open circuit), 50 Ω source impedance (−10 V to +10 V, 0.5 to 10 V<sub>p-p</sub> into 50 Ω)}} | |||
{{Spec|Trigger/Gate input|Sensitivity 80 mV<sub>p-p</sub> to ≥10 MHz, 250 mV<sub>p-p</sub> to ≥50 MHz at 50 Ω impedance, max. ±5 V<sub>peak</sub>; 1 MΩ // 20 pF optionally selectable (internal switch), max. ±20 V<sub>peak</sub>}} | |||
{{EndSpecs}} | {{EndSpecs}} | ||
==Rear Interface== | |||
(right-hand plug-in slot as viewed from front) | |||
* 27B/28B(GND) Trig output (complement polarity installed; for normal polarity, front panel input requires optional cable and front output disconnection) ''[note error on manual p.1-12; table 1-13 is correct]'' | |||
* 24B/25B(GND) Trig input (with optional cable, front panel input must be disconnected) | |||
* 25A/26A(GND) Amplitude Monitor (from output via 27 kΩ) | |||
* 22A External Low Level Control Input (requires internal jumper and trim) | |||
* 22B External High Level Control Input (requires internal jumper and trim) | |||
Custom connection solder pads ae available on the left plug-in slot, which is otherwise used only for hte associated pass transistors in the mainframe. | |||
==References== | ==References== | ||
* Designs by the Masters | * Designs by the Masters – ±20 V, 5 ns, 50 Ω Amplifier (detailed discussion of the PG508 output stage). Horowitz & Hill, Art of Electronics - The x-Chapters, p.150+ | ||
==Pictures== | ==Pictures== |