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It had a 4-bit data path width and 12 address bits and a minimum cycle time of 10.8 µs. It was packaged in a 16-pin DIL with multiplexed bus signals. | It had a 4-bit data path width and 12 address bits and a minimum cycle time of 10.8 µs. It was packaged in a 16-pin DIL with multiplexed bus signals. | ||
==Used in== | |||
* [[7L18]] | |||
==Links== | ==Links== |