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Revision as of 11:02, 9 January 2022

126 bytes removed ,  9 January 2022
more relevant key specs
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(more relevant key specs)
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* [http://w140.com/smb/df1_sm.pdf Tektronix DF1 Manual] (OCR)
* [http://w140.com/smb/df1_sm.pdf Tektronix DF1 Manual] (OCR)
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The '''Tektronix DF1''' is a display formatter for use with the [[7D01]] logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared.
The '''Tektronix DF1''' is a display formatter for use with the [[7D01]] logic analyzer. It adds "data domain displays" (binary, octal and hexadecimal state tables, and a function map display) to the 7D01's time-domain display. It can store a reference table, to which the captured data can be compared.  The [[DF2]] is essentially a DF1 with an extra key ("Menu") and additional ROM supporting GPIB diagnostics.


Project manager for the DF1 was [[Murlan Kaufman]].
Project manager for the DF1 was [[Murlan Kaufman]].
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{{BeginSpecs}}
{{BeginSpecs}}
{{Spec | External Read Clock |
{{Spec | Memory | One reference table memory, same as 7D01 capacity (max. 16 channels at 254 bits/ch) }}
* Frequency Range 100 kHz to 500 kHz
{{Spec | Display modes |
* Duty Cycle 50% within 5%.}}
* State table: Hexadecimal, octal, or binary formats; two tables (reference, 7D01 memory) of 17 lines of 16-bit words
{{Spec | Display |  
* Map: Dot display of the 16 data channels in X-Y coordinate points. Each dot location represents one possible combination of up to 16 inputs to the 7D01/
* Vertical Size — Adjustable from 6.9 div or less to at least 8.1 div from the top of the first line of DF1 readout to the bottom of the last line of DF1 readout.
* Timing: Standard 7D01 display – 4, 8 or 16 bits
* Vertical Position — Adjustable to vertical center of display area in any calibrated 7000-series mainframe.
}}
* Horizontal Position — Adjustable to horizontal center of display area in any calibrated 7000-series mainframe.}}
{{Spec | Reset output | Positive 100 μs pulse, ≤0.4 V / ≥2.4 V }}
{{Spec | Output Signals |  
* Reset Logic Voltage Level — LO: +0.4 V or less at 2 mA.  HI: at least +2.4 V at 2 mA.
* Waveshape — Positive-going rectangular pulse.
* Duration — 100 μs within 50 μs when used with the 7D01 internal read clock.}}
{{EndSpecs}}
{{EndSpecs}}


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==Pictures==
==Pictures==
<gallery>
<gallery>
Tek df1 front.JPG|Front
Tek df1 front.JPG|Front
Retrieved from "https://w140.com/tekwiki/wiki/Special:MobileDiff/71616"

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