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7D01: Difference between revisions
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Tek_7D01_Memory.jpg | 7D01 Memory Board | Tek_7D01_Memory.jpg | 7D01 Memory Board | ||
Tek_7D01_timing.jpg | Standalone 7D01 Timing Diagram (using mainframe readout) | Tek_7D01_timing.jpg | Standalone 7D01 Timing Diagram (using mainframe readout) | ||
Tek_7D01-DF01_timing.jpg | 7D01 + [[DF1]] | Tek_7D01-DF01_timing.jpg | 7D01 + [[DF1]]/DF2 Timing Diagram (readout from DF) | ||
Tek_7D01-DF01_table.jpg | 7D01 + [[DF1]] | Tek_7D01-DF01_table.jpg | 7D01 + [[DF1]]/DF2 State Table | ||
</gallery> | </gallery> | ||