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7B80: Difference between revisions
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The companion delaying timebase for use in 4-slot mainframes is the [[7B85]]. The [[7B50A]] is essentially a 7B80 with its fastest calibrated sweep rate limited to 5 ns/div. | The companion delaying timebase for use in 4-slot mainframes is the [[7B85]]. The [[7B50A]] is essentially a 7B80 with its fastest calibrated sweep rate limited to 5 ns/div. | ||
The | From Tekscope Vol.8 No.1, 1976: | ||
<blockquote> | |||
[[Les Larson]] developed the trigger circuitry and served as Project Manager for the 7B80 and 7B85. | |||
The sweeps were designed by [[Bruce Hofer]] and the DVM and related logic by [[Paul Farley]]. Much credit is due [[Art Metz]] for his work on the trigger input 1C which includes the peak-to-peak automatic trigger circuitry. | |||
[[Gene Andrews]], Program Manager, provided overall direction for the project. | |||
</blockquote> | |||
{{BeginSpecs}} | {{BeginSpecs}} | ||
{{Spec | Sweep | 10 ns/Div to 5 s/Div (1–2–5), ×10 magnifier (down to 1 ns/Div), variable sweep (up to ×2.5) and holdoff (up to ×2 sweep lengths at 20 ms/Div and faster)}} | {{Spec | Sweep | 10 ns/Div to 5 s/Div (1–2–5), ×10 magnifier (down to 1 ns/Div), variable sweep (up to ×2.5) and holdoff (up to ×2 sweep lengths at 20 ms/Div and faster)}} | ||