7D02: Difference between revisions

7D02 (view source)

61 bytes removed , 16 August 2023

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 {{BeginSpecs}}
 {{Spec | Channels | up to 52  - 28 (optionally 44) synchronous, 8 sync or async (timing option) }}
-{{Spec | Inputs  | (standard 7D02) 8 Data, 16 Address, 10 Control, 1 Ext. Trigger }}
+{{Spec | Inputs  | (standard 7D02) 8 data, 16 address, 10 control, 1 ext. trigger }}
 {{Spec | Memory | 256 words }}
-{{Spec | Timing option | 8 channels, 255 word acquisition memory, 255 word glitch memory, 9 bit word recognizer; sampling 5 ms to 20 ns; [[P6451]] logic probe }}
 {{Spec | Sampling Rate | up to 10 MHz }}
 {{Spec | Options |
-* Option 01 − Timing Option: provides 8 additional asynchronous channels with sample rates up to 50 MHz using [[P6451]] probe
+* Option 01 − Timing: Adds 8 additional asynchronous channels with sampling rates from 5 ms to 20 ns (up to 50 MHz) using a [[P6451]] logic probe;<br />255-word acquisition memory, 255-word glitch memory, 9-bit word recognizer
-* Option 03 − Expansion: Adds 8 Data and 8 Address lines to 7D02, required for 16 bit microprocessors.
+* Option 03 − Expansion: Adds 8 data and 8 address lines to 7D02, required for 16 bit microprocessors.
 }}
 {{EndSpecs}}