7D01: Difference between revisions

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7D01 (view source)

Revision as of 08:32, 23 September 2023

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When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen [[7603N]].
When combined with an optional [[DF1]] or [[DF2]] display formatter (attached to the left of the 7D01 through a [[D-sub connector|DD-50 connector]]), data domain displays (state table and map) become available, and the formatter generates the readout in timing diagram mode, allowing a 7D01 with display formatter to be used in mainframes without readout, e.g. the large-screen [[7603N]].
The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier.
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. 
The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
There is no internal glitch detector, but a separate [[DL2]] or [[DL502]] latch plug-in can be used to stretch short pulses ≥5 ns to the clock period.
The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.


Project manager for the 7D01 was [[Murlan Kaufman]].  Project leader was [[Keith Taylor]], with [[Morris Green]] and [[Jeff Bradford]] doing electrical design, and [[Ed Wolf]] mechanical design. [[Wendell Damm]] worked on the active probe.
Project manager for the 7D01 was [[Murlan Kaufman]].  Project leader was [[Keith Taylor]], with [[Morris Green]] and [[Jeff Bradford]] doing electrical design, and [[Ed Wolf]] mechanical design. [[Wendell Damm]] worked on the active probe.
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==Acquisition==
The 7D01 acquires data asynchronously using an internal clock from 10 ns to 50 ms per sample, or synchronously based on an external clock.
The 9<sup>th</sup> channel on the first probe serves as an external clock input, that on the second probe as an external qualifier.
A built-in word recognizer can trigger on any combination of the 16 data signals, plus the probe and external qualifier inputs. 
The recognizer's output is available to trigger an external unit, e.g. when the 7D01 is combined with amplifier and timebase plug-ins in a 4-bay mainframe.
The input logic threshold can be set to 1.4 V for TTL, a screwdriver-adjustable voltage (VAR) between −12 V and +12 V, or a mixed mode (TTL-VAR) where the first probe (0–7, CLK) is set to the variable voltage, and the second probe (9−15, QUAL) to 1.4 V.
There is no internal glitch detector, but a separate [[DL2]] or [[DL502]] latch plug-in can be used to stretch short pulses ≥5 ns to the clock period.
The latch plugs in between the P6451 probes and the 7D01's inputs, and receives the sample clock from the 7D01's Store Clock output.


==Internals==
==Internals==
Retrieved from "https://w140.com/tekwiki/wiki/Special:MobileDiff/85689"

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