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DC505: Difference between revisions
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Data is output serially by digit. | Data is output serially by digit. | ||
==Internals== | |||
An internal VCO, phase-locked to the 1 MHz master, produces a 100 MHz input to the counter chain for timing measurements. | |||
The DC505A uses a mix of ECL and TTL dividers and logic, and a [[Mostek MK5007]] four-decade counter/latch/multiplexer (U700). Unlike the similarly-specified [[7D15]], it employs no Tek made custom ICs. | |||
The first counter decade is implemented as a divide-by-2 ECL flip-flop (U342, MC1670) followed by a five-stage ring counter made with MC10131 ECL flipflops, and some logic to BCD-encode the count result. A similar circuit exists in the reference divider chain. | |||
In the power supply, the +5 V section, controlled by a 723, uses the mainframe's NPN pass transistor and includes a zener/SCR crowbar circuit. A discrete regulator using the PNP pass transistor produces - V from the -33 V rail. | |||
==Pictures== | ==Pictures== | ||